221–230 of 268 posts
Side note: when people complain about the military budget, projects like these should be noted. Political reality in America, today, is military R&D and jobs programs are easier to fund than civilian ones; so that’s where projects go to live.
This $100M research project is equivalent to about one fighter plane (without the ammunition, I guess). Imagine what we could fund for the cost of an aircraft carrier.
I also thought I'd try to answer some questions that I've seen in the comments. Disclaimer: as a lowly PhD student I am only privy to some information. I'm answering to the best of my knowledge.
1) As mentioned by hardwarefriend, synthesis tools are standard in ASIC/FPGA design flows. However, chip design currently often still takes a lot of manual work and/or stitching together of tools. The main goal of the compiler is to create a push-button solution. Designing a new chip should be as simple as cloning a design from GitHub and calling "make" on the silicon compiler.
2) Related to (1). The focus is on automation rather than performance. We are okay with sacrificing performance as long as compiler users don't have to deal with individual build steps.
3) There should be support for both digital, analog, and mixed-signal designs.
4) Rest assured that people are aware of yosys and related tools. In fact, Clifford was present at the event :-) Other (academic) open source EDA tools include the ABC for logic synthesis & verification, the EPFL logic synthesis libraries (disclaimer: co-author), and Rsyn for physicial design. There are many others, I'm certainly not familiar with all of them. Compiling a library of available open source tools is part of the project.
Edit: to be clear, WOSET has been planned, but will be held in November. Submissions are open until August 15.
Earlier quoted context omitted.
How you know that Ukraine still doesn't have nuclear weapons?
Because I assume that the Russians, when they armed it (In Soviet times), and then disarmed it (In post-Soviet times), could count up to, and back down from twenty. If they still have weapons, they sure as hell haven't been using their existence as a deterrent. The whole point of having nukes is letting potential aggressors know that you have them, and that, if attacked, you may be crazy enough to use them.
You must know that Ukraine was attacked 4 years ago. So the "whole point" is not applicable in this case.
Earlier quoted context omitted.
Uh, for 90nm you should be in the 4-digit range for a hand full of prototypes.
Oh yea I was totally exaggerating since obviously the prices vary tremendously upon the what you are trying to do. I’ve previously worked for a semiconductor company, so there is sort of a “you can pay as much as you want” option always avail if you want a super awesome mixed signal chip. For the general public, do you have a particular place you are aware of that you would pay the 4 digits for the mask plus few prot…
Earlier quoted context omitted.
> the backoffice engineers would make a build that fixed only those bugs Makes perfect business sense! Those customers didn't pay to get those bugs fixed, so why should they get the fixes??? /s Holy moly.
Seems very similar to how Restaurants and grocery stores throw food out instead of giving it to shelters and homeless people. It’s a common corporate policy in the US. The only justification seems to be that if they gave it away, they might miss out on some otherwise potential sales.
It stinks badly, but is a sad reality.
Earlier quoted context omitted.
You couldn't be any more dead-on. EDA feels like Scientology, where with every level closer to the core you first need to invest half your life savings + a firstborn. I have an FPGA lying on my desk I can do barely anything interesting with because there are no open-source cores for even simple things like USB3.1 controllers or Thunderbolt or pretty much any interesting bus. Protocols are strongly guarded open secret…
USB 3.1 pushes data at 10Gbps. Do you have any idea how much black magic it takes to do that? Try writing an FPGA SDRAM controller that reliably operates across frequency, voltage, and temperature at 150 MHz. It is doable but a challenge with the common xilinx boards that are sold to hobbyists for $80. If you can do that, then think about designing a circuit which operates 20 times faster, and negotiates a protocol w…
I doubt most projects need the full 10gibts. What if they only need 750mbits? That's unfortunately not possible without USB 3.1. The alternative to USB 3.1 (Gen 1 or 2 doesn't matter) is USB 2.0 which only can do 480mbits.
Earlier quoted context omitted.
The participating companies makes chips that requires a huge amount of resources to make them happen: design engineering time, CAD software, tape-out cost, validation engineering time, ... The CAD software is expensive, but it's not barrier of entry expensive compared to design engineering time, tape-out cost etc. If the CAD software cost gets reduced, it would result in a cost reduction of all companies involved whi…
From the article: "If successful, the programs “will change the economics of the industry,” enabling companies to design in relatively low-volume chips that would be prohibitive today. "
Earlier quoted context omitted.
> the backoffice engineers would make a build that fixed only those bugs Makes perfect business sense! Those customers didn't pay to get those bugs fixed, so why should they get the fixes??? /s Holy moly.
I think a reasonable explanation may be that other customers possibly have come to unknowingly rely on some of the bugs. Shipping a fix of all the bugs could actually break their code!
"Most importantly, we have to change the culture of hardware design. Today, we don’t have open sharing … " This, to the 100th power. The culture in the EDA industry is stuck in the 1950's when it comes to collaboration and sharing, it's very frustrating for newcomers and people who want to learn the trade. As was pointed out by someone in another hardware related HN thread, what can you expect from an industry that i…
>> "Most importantly, we have to change the culture of hardware design. Today, we don’t have open sharing … " I'll have popcorn ready for the eventuality where IP blocks are widely available under GPL type of FOSS licenses and Intel|AMD|ARM|TI|... is eventually found to include one or more of those open sourced blocks with incompatible license in their chips.
First off, the RISC-V community is based on the open ISA. There are several open implementations of the ISA. And the RISC-V community is meaking good headways in developing open tools, peripheral cores etc.
Secondly there are at least two attempts at collecting and tracking open cores for FPGA- and ASIC-implementations.
LibreCores is the newer project. They have collected quite a few projects:
https://www.librecores.org/ https://www.librecores.org/project/list
Related to LibreCores is the SoC-builder and core package handler Fusesoc by Olof Kindgren. Fusesoc makes creating your SoC easy:
https://github.com/olofk/fusesoc
The older project is OpenCores. OpenCores has been quite tightly related to the OpenRISC CPU core, the wishbone set of on-chip interconnect solutions. They have been used in many FPGAs and ASICs
https://opencores.org/ https://openrisc.io/
Then you have projects like Cryptech that develops a complete, totally open, Hardware Security Module capable of doing certificate signing, OpenDNSSEC signing etc. The Cryptech Alpha design from PCB to FPGA cores and SW including pkcs11 handling is open. The project has amassed quite a few cores. The PCB design is available in kiCAD. (disclaimer: I'm part of the Cryptech core team doing a lot of the FPGA design work.)
https://cryptech.is/ https://trac.cryptech.is/wiki/GitRepositories
Speaking of tools like KiCAD, there are aqtually quite a few open tools for HW design. For simuation there are Icarus Verilog, Verilator, cver for example. They might not be as fast as VCS by Synoptsys. But they do work. I use them daily.
http://iverilog.icarus.com/ https://www.veripool.org/projects/verilator/wiki/Intro
For synthesis, P&R the state is less good. For implementation in Altera and Xilinx devices you currently have to use the cost free tools from the vendors. But there is work ongoing to reverse engineer Xilinx Spartan devices. I don't know the current state though.
But what has been reverse engineered are the ICE40 FPGA devices from Lattice. And for these you can use the open tool Yosys by Clifford Wolf (also mentioned below by someone else).
And if you are looking for open implementations of crypto functions etc I have quite a few on Github and try to develop more all the time:
The sha256 and aes cores has been used in quite a few FPGA and ASIC designs. Right now I'm working on completing cores for the Blake2b and Blake2s hash functions.
I agree that we in the HW community is waay behind the SW community in terms of open tools, libraries (i.e. cores). But it is not totally rotten, and it is getting better. RISC-V is to me really exciting.
Earlier quoted context omitted.
How was that different than ideas found in object oriented programming?
There were folks that believe you could instantiate objects graphically, and just connect them together and wire them up. Take a look at Java Spring Beans, which let you describe object instances through XML that either defines an object instance or wires up other instances together.
A review with screenshots : https://www.javaworld.com/article/2076574/developer-tools-id...