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Darpa invests $100M in a silicon compiler

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Re: Darpa invests $100M in a silicon compiler

#81

Post by civilitty »

solarkraft wrote: post #71
civilitty wrote: post #58

Earlier quoted context omitted.

> If AMD open sourced all the design aspects of their chips, I would have to get a loan to build 100 million fab to have any practical manner to enjoy it? Try $1 to 5 billion. We're talking about something that over half of all extant nation states wouldn't be able to pull off without devoting 10-50% of their annual GDP to the project.

Even the large designers (AMD, Apple, Mediatek) don't have their own fabs. You would "just" need to order a design made - probably for hundreds of thousands of chips to make any sense. Is there information on what this step would actually require?

First, you have to choose your feature size and manufacturer based on your specs because that will lock down your available cell library. Cell libraries are an abstraction over the masks/dopants and describe how to fab the transistors and higher level logic gates, made by each manufacturer for each feature size. STM, TSMC, Global Foundries, etc. have their own cell libraries and each process node gets a different one (there could also be different libraries for consumer, medical, automotive, etc.). If your design isn't pushing the physical limits of your chosen process, you can usually use a standard cell library supported by your synthesizer so that you can stay in HDLs instead of tweaking masks.

Once you've finished your design (I'll leave this as an exercise to the reader :)), you'll start a back and forth with the foundry which will run its own database of rules against your design and work with you to make tweaks that better fit their fab. After you agree on a final mask, you and the fab will run verification simulations and eventually, after several months, you'll get your chips with that new factory smell.

Yes, you can "just" order some chips made. I don't have the URLs off the top of my head but there are a few companies here in California that I've worked with. You can literally walk into their offices unannounced and if you have the money, they will start right then and there. If I remember correctly, in 2012 it cost about $100k to get started with STM's 45nm process (might have been 28nm by then, don't remember). Today, 28nm can cost as low as $4-12k if you're a Canadian researcher [1] - although that's almost certainly subsidized.

It all seems scary only because the process is so complex that no one person has a grasp on even a minor fraction of what's going on.

[1] https://www.cmc.ca/en/WhatWeOffer/Products/CMC-00200-02843.a...

Re: Darpa invests $100M in a silicon compiler

#82

Post by Aeolus98 »

I might be able to weigh in here.

Having these tools as open source and freely available is a huge deal for so many industries. I've worked with these tools at an academic level and now at a startup, and it's amazing the magnitude of this enabling technology. Just the tooling investment will be huge, making the core solvers and algorithms more accessible should spawn a whole new wave of startups/research in effectivley employing them. Just these days, I've heard of my friends building theorem provers for EVM bytecode to formally check smart contracts to eliminate bugs like these [0].

These synthesis tools roughly break down like this:

1. Specify your "program"

- In EDA tools, your program is specified in Verilog/VHDL and turns into a netlist, the actual wiring of the gates together.

- In 3D printers, your "program" is the CAD model, which can be represented as a series of piecewise triple integrals

- In some robots, your program is the set of goals you'd like to accomplish

In this stage, it's representation and user friendliness that is king. CAD programs make intuitive sense, and have the expressive power to be able to describe almost anything. Industrial tools will leverage this high-level representation for a variety of uses, like in the CAD of an airplane, checking if maintenance techs can physically reach every screw, or in EDA providing enough information for simulation of the chip or high-level compilation (Chisel)

2. Restructure things until you get to a an NP-complete problem, ideally in the form "Minimize cost subject to some constraints". The result of this optimization can be used to construct a valid program in a lower-level language.

- In EDA, this problem looks like "minimize the silicon die area used and layers used and power used subject to the timing requirements of the original Verilog", where the low level representation is the physical realization of the chip

- In 3D printers it's something like "minimize time spent printing subject to it being possible to print with the desired infill". Support generation and other things can be rolled in to this to make it possible to print.

Here, fun pieces of software in this field of optimization are used; Things like Clasp for Answer Set Programming, Gurobi/CPLEX for Mixed Integer programming or Linear programs, SMT/SAT solvers like Z3 or CVC4 for formal logic proving.

A lot of engineering work goes into these solvers, with domain specific extensions driving a lot of progress[1]. We owe a substantial debt to the researchers and industries that have developed solving strategies for these problems, it makes up a significant amount of why we can have nice things, from what frequencies your phone uses [2], to how the NBA decides to schedule basketball games. This is the stuff that really helps to have as public knowledge. The solvers at their base are quite good, but seeding them with the right domain-specific heuristics makes so many classes of real-world problems solvable.

3. Extract your solution and generate code

- I'm not sure what this looks like in EDA, my rough guess is a physical layout or mask set with the proper fuckyness to account for the strange effects at that small of a scale.

- For 3D printers, this is the emitted G-code

- For robots, it's a full motion plan that results in all goals being completed in an efficient manner.

[0] https://hackernoon.com/what-caused-the-latest-100-million-et...

[1] https://slideplayer.com/slide/11885400/

[2] https://www.youtube.com/watch?v=Xz-jNQnToA0&t=1s

Re: Darpa invests $100M in a silicon compiler

#83

Post by gascan »

detuur wrote: post #75
ur-whale wrote: post #29

Earlier quoted context omitted.

There are many NP complete problems where computer do vastly better than humans. But when it comes to EDA, the utterly closed-source culture of the industry has completely prevented what essentially amounts to a horde of smart people to work on the problem: no one - except a very small number insiders - even know what the problems are.

You couldn't be any more dead-on. EDA feels like Scientology, where with every level closer to the core you first need to invest half your life savings + a firstborn. I have an FPGA lying on my desk I can do barely anything interesting with because there are no open-source cores for even simple things like USB3.1 controllers or Thunderbolt or pretty much any interesting bus. Protocols are strongly guarded open secret…

because there are no open-source cores for even simple things like USB3.1 controllers or Thunderbolt

Those are hardly that simple. There exist entire companies whose function is designing such cores (and licensing them).

Re: Darpa invests $100M in a silicon compiler

#84

Post by slededit »

jacquesm wrote: post #76
slededit wrote: post #73

Earlier quoted context omitted.

You don't need XRay and your reflow oven can be a toaster oven. I do recommend a cheap microscope and a good pair of tweezers though. With this you can do 0.5mm pitch BGA although that is pushing it. I've made hundreds of prototypes this way. The fear of BGA parts is seriously overblown. The only real expensive part is the finer pitch parts will require tighter tolerances on the PCB which will take you out of the PCB…

Your comment reads as if you equate 'BGA' with 'SMD', a BGA is a ball grid array with up to 1,000 tiny pads that have been pre-dipped in solder. Your toaster isn't going to work.

BGA is actually easier than leaded SMD parts. The tiny leads tend to bridge easily. With BGA you can be up to half the pitch off and it will center itself. I actually only go for leadless and BGA now because anything else is more of a hassle.

It is a bit rude to assume I don't know what a BGA part is.

Re: Darpa invests $100M in a silicon compiler

#86

Post by hak8or »

jacquesm wrote: post #76
slededit wrote: post #73

Earlier quoted context omitted.

You don't need XRay and your reflow oven can be a toaster oven. I do recommend a cheap microscope and a good pair of tweezers though. With this you can do 0.5mm pitch BGA although that is pushing it. I've made hundreds of prototypes this way. The fear of BGA parts is seriously overblown. The only real expensive part is the finer pitch parts will require tighter tolerances on the PCB which will take you out of the PCB…

Your comment reads as if you equate 'BGA' with 'SMD', a BGA is a ball grid array with up to 1,000 tiny pads that have been pre-dipped in solder. Your toaster isn't going to work.

Yes, it will. Sure, it won't do wonders with 0.5mm pitch bga's, but 217 pin 0.8mm ones are doable even with a cheap Chinese hot air station. That's how I did these boards.

https://brainyv2.hak8or.com/

Re: Darpa invests $100M in a silicon compiler

#87

Post by phkahler »

WalterBright wrote: post #77
ur-whale wrote: post #14

"Most importantly, we have to change the culture of hardware design. Today, we don’t have open sharing … " This, to the 100th power. The culture in the EDA industry is stuck in the 1950's when it comes to collaboration and sharing, it's very frustrating for newcomers and people who want to learn the trade. As was pointed out by someone in another hardware related HN thread, what can you expect from an industry that i…

I designed the ABEL language back in the 80's for compiling designs targeted at programmable logic arrays and gate arrays. It was very successful, but it died after a decade or so. It'd probably be around today and up to date if it was open source. A shame it isn't. I don't even know who owns the rights to it these days, or if whoever owns it even knows they have the rights to it, due to spinoffs and mergers.

Have you looked at chisel?

Re: Darpa invests $100M in a silicon compiler

#88

Post by cosmon0t »

jayd16 wrote: post #47
JumpCrisscross wrote: post #5

Side note: when people complain about the military budget, projects like these should be noted. Political reality in America, today, is military R&D and jobs programs are easier to fund than civilian ones; so that’s where projects go to live.

We could fund this exact project through academic means. We choose to allot funds through the military.

A lot of academic funds have military roots?

Re: Darpa invests $100M in a silicon compiler

#89

Post by phkahler »

wrs wrote: post #74
ur-whale wrote: post #62

Earlier quoted context omitted.

The exact same arguments have been perused ad nauseam by old-timers in the software industry in the 80's and 90's when they clamored against open-source being anti-capitalist and un-american. Not sure how and why H/W is different.

Different level of liability. When GPL missteps are discovered in software, the offender can usually just re-release the software without the GPL code and move on. In hardware…it's soldered into a bunch of devices all over the place. Consider Intel taking a $475 million hit for the FDIV bug (requiring a hardware replacement) vs the invisible bugfixing through microcode (i.e., software) they do now.

You don't skip validation just because you use open source.

Re: Darpa invests $100M in a silicon compiler

#90

Post by civilitty »

slededit wrote: post #73
civilitty wrote: post #65

Earlier quoted context omitted.

What exactly do you mean by "getting started with FPGA on custom PCBs?" Have you made custom PCBs with high density BGAs before? Most non-trivial FPGAs (to me that means you can easily fit a decent softcore processor with space left over for your FPGA logic) will be ball grid arrays and almost impossible to DIY without xray inspection equipment and a reflow oven. You can get what you need for a few hundred $ on eBay…

You don't need XRay and your reflow oven can be a toaster oven. I do recommend a cheap microscope and a good pair of tweezers though. With this you can do 0.5mm pitch BGA although that is pushing it. I've made hundreds of prototypes this way. The fear of BGA parts is seriously overblown. The only real expensive part is the finer pitch parts will require tighter tolerances on the PCB which will take you out of the PCB…

With this you can do 0.5mm pitch BGA although that is pushing it.

If you have actually figured out how to consistently make boards with BGA-256/512 0.5mm pitch parts with just a toaster, I'd love to learn more about your technique. Even with professional inspection equipment and a pick and place, it's rarely worth the effort unless I have an imminent deadline.

For a beginner, I doubt the cost of trial and error would be cheaper than just having someone else do it. He could go with a larger pitch [edit: and smaller pin count] but I have never successfully introduced someone to FPGAs without a relatively huge chip capable of running a soft core closer to what they're used to with in general purpose computing.

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