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Darpa invests $100M in a silicon compiler

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Re: Darpa invests $100M in a silicon compiler

#71

Post by solarkraft »

civilitty wrote: post #58
ThinkBeat wrote: post #51

I don't quite get the open source angle in the comments here. If I managed to get my grubby hands on a moderately modern computer, I can use all manner of open source software and I can create wonderful new software. The barrier of entry is fairly low in rich countries. If AMD open sourced all the design aspects of their chips, I would have to get a loan to build 100 million fab to have any practical manner to enjoy…

> If AMD open sourced all the design aspects of their chips, I would have to get a loan to build 100 million fab to have any practical manner to enjoy it? Try $1 to 5 billion. We're talking about something that over half of all extant nation states wouldn't be able to pull off without devoting 10-50% of their annual GDP to the project.

Even the large designers (AMD, Apple, Mediatek) don't have their own fabs. You would "just" need to order a design made - probably for hundreds of thousands of chips to make any sense.

Is there information on what this step would actually require?

Re: Darpa invests $100M in a silicon compiler

#72

Post by civilitty »

hardwarefriend wrote: post #35
dalbasal wrote: post #18

I have questions, if anyone knows something about hardware. What would a "silicon compiler" let one do? What exactly gets easier/cheaper and what exactly could new chip designs yield?

It's difficult for me to be sure, since the article makes it sound as if they're attempting something novel, but synthesis tools are standard in ASIC/FPGA design flows. Currently, the best synthesis tools are closed-source and extremely expensive. Imagine the benefit of having gcc/clang be free software. That is the kind of effect that is at stake here. Usually, hardware designers will write RTL code (Verilog/VHDL) w…

To expand: compiling silicon isn't like compiling code even though it does use a hardware description language. Not only do all parts of your "code" all run at once, but you're also laying out physical transistors and mapping their connections. This is fundamentally an NP complete traveling salesman problem with an absurd exponential explosion of complexity - aka how do you route thousands or millions of connections that can't intersect on a 2D plane while still doing what the code describes. Oh and the fun part: unless you're careful, a change in a completely unrelated bit of code could break almost anything in the system by making it impossible to route connections without screwing up the timing of all the little bits.

There is no type checker that can deduce whether your design will work or not and then output machine language. At the end of the day, with silicon you have to actually figure out whether your design can be physically manufactured by running a long compiler process and then testing it, often with rigorous simulations before moving to the fab process.

Re: Darpa invests $100M in a silicon compiler

#73

Post by slededit »

civilitty wrote: post #65
mips_avatar wrote: post #38

Earlier quoted context omitted.

Any tips on getting started with FPGA on custom pcbs?

What exactly do you mean by "getting started with FPGA on custom PCBs?" Have you made custom PCBs with high density BGAs before? Most non-trivial FPGAs (to me that means you can easily fit a decent softcore processor with space left over for your FPGA logic) will be ball grid arrays and almost impossible to DIY without xray inspection equipment and a reflow oven. You can get what you need for a few hundred $ on eBay…

You don't need XRay and your reflow oven can be a toaster oven. I do recommend a cheap microscope and a good pair of tweezers though. With this you can do 0.5mm pitch BGA although that is pushing it. I've made hundreds of prototypes this way.

The fear of BGA parts is seriously overblown. The only real expensive part is the finer pitch parts will require tighter tolerances on the PCB which will take you out of the PCB batch services price tier.

edit: toaster oven, not toaster

Re: Darpa invests $100M in a silicon compiler

#74

Post by wrs »

ur-whale wrote: post #62
rixrax wrote: post #49

Earlier quoted context omitted.

>> "Most importantly, we have to change the culture of hardware design. Today, we don’t have open sharing … " I'll have popcorn ready for the eventuality where IP blocks are widely available under GPL type of FOSS licenses and Intel|AMD|ARM|TI|... is eventually found to include one or more of those open sourced blocks with incompatible license in their chips.

The exact same arguments have been perused ad nauseam by old-timers in the software industry in the 80's and 90's when they clamored against open-source being anti-capitalist and un-american. Not sure how and why H/W is different.

Different level of liability. When GPL missteps are discovered in software, the offender can usually just re-release the software without the GPL code and move on. In hardware…it's soldered into a bunch of devices all over the place. Consider Intel taking a $475 million hit for the FDIV bug (requiring a hardware replacement) vs the invisible bugfixing through microcode (i.e., software) they do now.

Re: Darpa invests $100M in a silicon compiler

#75

Post by detuur »

ur-whale wrote: post #29
darzu wrote: post #21

Earlier quoted context omitted.

They have. The problem is that efficient silicon layout is NP-complete and automated tools can't do better than humans today. At best they can assist and detect certain classes of errors. I'm sure Intel has invested more than $100 million on tooling by now.

There are many NP complete problems where computer do vastly better than humans. But when it comes to EDA, the utterly closed-source culture of the industry has completely prevented what essentially amounts to a horde of smart people to work on the problem: no one - except a very small number insiders - even know what the problems are.

You couldn't be any more dead-on. EDA feels like Scientology, where with every level closer to the core you first need to invest half your life savings + a firstborn. I have an FPGA lying on my desk I can do barely anything interesting with because there are no open-source cores for even simple things like USB3.1 controllers or Thunderbolt or pretty much any interesting bus. Protocols are strongly guarded open secrets where everyone in the industry knows how they work (like MIPI for example) but God Forbid anyone outside the industry might show interest in them. Then you first need a $100k annual membership to the foundation and need to sign and NDA with your blood and that of the next three kin in line.

There's a cargo cult confidentiality that achieves absolutely nothing if not completely frustrating out anyone who tries their best to keep their interest in it alive.

Re: Darpa invests $100M in a silicon compiler

#76

Post by jacquesm »

slededit wrote: post #73
civilitty wrote: post #65

Earlier quoted context omitted.

What exactly do you mean by "getting started with FPGA on custom PCBs?" Have you made custom PCBs with high density BGAs before? Most non-trivial FPGAs (to me that means you can easily fit a decent softcore processor with space left over for your FPGA logic) will be ball grid arrays and almost impossible to DIY without xray inspection equipment and a reflow oven. You can get what you need for a few hundred $ on eBay…

You don't need XRay and your reflow oven can be a toaster oven. I do recommend a cheap microscope and a good pair of tweezers though. With this you can do 0.5mm pitch BGA although that is pushing it. I've made hundreds of prototypes this way. The fear of BGA parts is seriously overblown. The only real expensive part is the finer pitch parts will require tighter tolerances on the PCB which will take you out of the PCB…

Your comment reads as if you equate 'BGA' with 'SMD', a BGA is a ball grid array with up to 1,000 tiny pads that have been pre-dipped in solder. Your toaster isn't going to work.

Re: Darpa invests $100M in a silicon compiler

#77

Post by WalterBright »

ur-whale wrote: post #14

"Most importantly, we have to change the culture of hardware design. Today, we don’t have open sharing … " This, to the 100th power. The culture in the EDA industry is stuck in the 1950's when it comes to collaboration and sharing, it's very frustrating for newcomers and people who want to learn the trade. As was pointed out by someone in another hardware related HN thread, what can you expect from an industry that i…

I designed the ABEL language back in the 80's for compiling designs targeted at programmable logic arrays and gate arrays. It was very successful, but it died after a decade or so.

It'd probably be around today and up to date if it was open source. A shame it isn't. I don't even know who owns the rights to it these days, or if whoever owns it even knows they have the rights to it, due to spinoffs and mergers.

Re: Darpa invests $100M in a silicon compiler

#78

Post by jimmyswimmy »

slededit wrote: post #73
civilitty wrote: post #65

Earlier quoted context omitted.

What exactly do you mean by "getting started with FPGA on custom PCBs?" Have you made custom PCBs with high density BGAs before? Most non-trivial FPGAs (to me that means you can easily fit a decent softcore processor with space left over for your FPGA logic) will be ball grid arrays and almost impossible to DIY without xray inspection equipment and a reflow oven. You can get what you need for a few hundred $ on eBay…

You don't need XRay and your reflow oven can be a toaster oven. I do recommend a cheap microscope and a good pair of tweezers though. With this you can do 0.5mm pitch BGA although that is pushing it. I've made hundreds of prototypes this way. The fear of BGA parts is seriously overblown. The only real expensive part is the finer pitch parts will require tighter tolerances on the PCB which will take you out of the PCB…

Agreed, if you meant a toaster oven. It does take precise temperature control if you want any chance at reliability. And a fine touch. It's easy to line the whole thing up one row off and have to scrap the part, which is a bummer if you can't re ball it.

Re: Darpa invests $100M in a silicon compiler

#79

Post by v_lisivka »

GW150914 wrote: post #63
v_lisivka wrote: post #55

Earlier quoted context omitted.

Ukraine is still alive after 4 years of war with Russia. Relax.

They’re at war with Russia because they gave up their nuclear weapons. No one is invading a nuclear power, which I think is the point the post you’re responding to was making.

How you know that Ukraine still doesn't have nuclear weapons?

Re: Darpa invests $100M in a silicon compiler

#80

Post by extrapickles »

jacquesm wrote: post #76
slededit wrote: post #73

Earlier quoted context omitted.

You don't need XRay and your reflow oven can be a toaster oven. I do recommend a cheap microscope and a good pair of tweezers though. With this you can do 0.5mm pitch BGA although that is pushing it. I've made hundreds of prototypes this way. The fear of BGA parts is seriously overblown. The only real expensive part is the finer pitch parts will require tighter tolerances on the PCB which will take you out of the PCB…

Your comment reads as if you equate 'BGA' with 'SMD', a BGA is a ball grid array with up to 1,000 tiny pads that have been pre-dipped in solder. Your toaster isn't going to work.

You can use a toaster, but your yield will be poor. Slapping some insulation on the oven and a PID controller will improve things significantly.

If you screw up the solder job, you can use a hot air gun to remove the BGA part, reball it (using a stencil, fairly cheap if its a common package), then try reflowing again.

If you practice for a few hours on scrap electronics, you can get good enough at it.

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