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FPGAs becoming more SoC-like

semiengineering.com

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Re: FPGAs becoming more SoC-like

#11

Post by tails4e »

codeflo wrote: post #4
arghwhat wrote: post #3

Earlier quoted context omitted.

It wasn't a question. ASIC isn't the tool for large volume, it's the tool for when you can accept a several year turnaround time for revisions, vs. a day or two. ASIC > FPGA... except if your design changes, ever. If anything high-bandwidth or design intensive is going on, you're definitely going to revise your design many times. FPGA's are massively on the rise (although slightly less so than Xilinx would like), and…

What's the tooling like for a typical, production-quality FPGA project nowadays? Last I checked, which is admittedly a couple of years ago (and I didn't dive in very deeply), it was a horrible mix of badly programmed vendor-specific Windows-only GUI tools. It seemed a lot like the embedded processor market where every single vendor has their own lock-in strategy and the whole ecosystem suffers for it. Has this improv…

Vivado us actually very good for EDA, and especially for one you can get for free (webpack). Compare it to design compiler for basic synthesis- now that is an ugly gui! Vivado had made great strides to integrate ip/rtl/synthesis/pnr/debug with cross probing between stages and great visual presentation of results. Try do any of this with 'industry standard' tools like design compiler and you will see just how good it is comparatively.

Re: FPGAs becoming more SoC-like

#12

Post by tails4e »

xfer wrote: post #10
lnsru wrote: post #5

Earlier quoted context omitted.

The colleagues are telling me, that this ugly GUI works nowadays under Linux too. You also can script much using tcl commands. I have it running on Windows and it works somehow, but I am not happy user:-/

Xilinx Vivado is not ugly; but resource heavy; so most people stick to tcl scripting.

Agreed it's a very well designed gui, but seems to gobble memory. If you have a 32gb linux machine it's excellent.

Re: FPGAs becoming more SoC-like

#14

Post by stochastic_monk »

aylons wrote: post #8
codeflo wrote: post #4

Earlier quoted context omitted.

What's the tooling like for a typical, production-quality FPGA project nowadays? Last I checked, which is admittedly a couple of years ago (and I didn't dive in very deeply), it was a horrible mix of badly programmed vendor-specific Windows-only GUI tools. It seemed a lot like the embedded processor market where every single vendor has their own lock-in strategy and the whole ecosystem suffers for it. Has this improv…

Windows only tools? You must have been using Altera options (I briefly maintained the page for Quartus compatibility at wine, circa 2004). Even them have had Linux support for a while, Xilinx has Linux support for as far as I remember, at least some ten years. The ecosystem is terrible, I agree with you. However, the lock in is restricted for the final synthesis part. Simulation is mostly done with (very expensive) t…

I know someone who’s implemented some string algorithms for FPGA with verilog. Is writing the code distinct from the tooling you’re referring to, or simply an open source flavor of deployment? I haven’t done any FPGA work.

Re: FPGAs becoming more SoC-like

#15

Post by lnsru »

tails4e wrote: post #12
xfer wrote: post #10

Earlier quoted context omitted.

Xilinx Vivado is not ugly; but resource heavy; so most people stick to tcl scripting.

Agreed it's a very well designed gui, but seems to gobble memory. If you have a 32gb linux machine it's excellent.

Going from IP catalog to pin planner is not the easiest task. Or setting bitstream properties. Some settings are accessible from special locations, and this isn’t very intuitive. It’s easy when you know all these details.

Re: FPGAs becoming more SoC-like

#16

Post by thesz »

Article says "CPU does not fit FPGA synthesis very well and uses almost whole thing".

People serious about prototyping usually get daughterboards for FPGA and/or FPGA stacks specifically to prototype big things with CPUs. The buses can go outside of main FPGA with CPU and into other things. I know at least one big SoC project which went that way.

I also think that having an ARM core in FPGA is a vendor lock in. For example, you cannot use AMBA/APB/AXB and other ARM buses with ARM CPU core in your design without paying ARM for license for these buses. It is not clear to me whether Zynq users have to pay for these buses and it may be case that they have to. Finally, ARM core in the prototype naturally extends into ARM core in the final product.

ARM itself is not very nice design from contemporary point of view. I expressed my dissatisfaction with ARM ISA many times here and just let me start with two points: 1) ARM is not RISC (multiregister load/store execute in several clocks) and 2) too much of initial design of first ARM (which was not planned for longterm evolution) is visible in ISA.

Basically, they put outdated (even for 2010) core design and used valuable silicon area so users have to use that instead of much more capable contemporary designs. Instead of trying to figure out how to change typical FPGA elements and layouts for CPUs to be more synthesable (which may bring benefits in other places), they decided to use that ARM thing.

I am deeply disappointed with that path.

Re: FPGAs becoming more SoC-like

#17

Post by kingosticks »

oneplane wrote: post #13

But isn't it becoming more like "SoCs gaining FPGA cores"? I know traditional FPGAs got hard CPU cores added, but from the CPU perspective the FPGA core is the new thing.

This article mentions that but doesn't give any details. Annoying since that's the interesting bit.

Re: FPGAs becoming more SoC-like

#18

Post by baybal2 »

codeflo wrote: post #4
arghwhat wrote: post #3

Earlier quoted context omitted.

It wasn't a question. ASIC isn't the tool for large volume, it's the tool for when you can accept a several year turnaround time for revisions, vs. a day or two. ASIC > FPGA... except if your design changes, ever. If anything high-bandwidth or design intensive is going on, you're definitely going to revise your design many times. FPGA's are massively on the rise (although slightly less so than Xilinx would like), and…

What's the tooling like for a typical, production-quality FPGA project nowadays? Last I checked, which is admittedly a couple of years ago (and I didn't dive in very deeply), it was a horrible mix of badly programmed vendor-specific Windows-only GUI tools. It seemed a lot like the embedded processor market where every single vendor has their own lock-in strategy and the whole ecosystem suffers for it. Has this improv…

Lattice was the one

Re: FPGAs becoming more SoC-like

#19

Post by [deleted] »

stochastic_monk wrote: post #14
aylons wrote: post #8

Earlier quoted context omitted.

Windows only tools? You must have been using Altera options (I briefly maintained the page for Quartus compatibility at wine, circa 2004). Even them have had Linux support for a while, Xilinx has Linux support for as far as I remember, at least some ten years. The ecosystem is terrible, I agree with you. However, the lock in is restricted for the final synthesis part. Simulation is mostly done with (very expensive) t…

I know someone who’s implemented some string algorithms for FPGA with verilog. Is writing the code distinct from the tooling you’re referring to, or simply an open source flavor of deployment? I haven’t done any FPGA work.

[deleted]
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