FPGAs becoming more SoC-like
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FPGAs becoming more SoC-like
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Re: FPGAs becoming more SoC-like
#2No. There is a more suitable tools now for every problem. Large volume - ASIC, and you can also put few ARM cores inside. Something highly integrated - pick ZynQ. There are dozen different solutions for all the problems starting with big FPGA with couple softcore processors going to cheap spartan 7 device and going to tiny and dirt cheap Lattice chip for glue logic or IO expansion. Tools might be better, but this problem will be solved in the future for sure.
Re: FPGAs becoming more SoC-like
#3No. There is a more suitable tools now for every problem. Large volume - ASIC, and you can also put few ARM cores inside. Something highly integrated - pick ZynQ. There are dozen different solutions for all the problems starting with big FPGA with couple softcore processors going to cheap spartan 7 device and going to tiny and dirt cheap Lattice chip for glue logic or IO expansion. Tools might be better, but this pro…
It wasn't a question.
ASIC isn't the tool for large volume, it's the tool for when you can accept a several year turnaround time for revisions, vs. a day or two. ASIC > FPGA... except if your design changes, ever. If anything high-bandwidth or design intensive is going on, you're definitely going to revise your design many times.
FPGA's are massively on the rise (although slightly less so than Xilinx would like), and they all are effectively "SoC like", with DSPs, transceivers, hard IP's probably being a majority of the chip by now.
Zynq is a cute little chip, but with Intel's coming CPU-embedded FPGA's, thing will kick off even more.
Re: FPGAs becoming more SoC-like
#4No. There is a more suitable tools now for every problem. Large volume - ASIC, and you can also put few ARM cores inside. Something highly integrated - pick ZynQ. There are dozen different solutions for all the problems starting with big FPGA with couple softcore processors going to cheap spartan 7 device and going to tiny and dirt cheap Lattice chip for glue logic or IO expansion. Tools might be better, but this pro…
It wasn't a question. ASIC isn't the tool for large volume, it's the tool for when you can accept a several year turnaround time for revisions, vs. a day or two. ASIC > FPGA... except if your design changes, ever. If anything high-bandwidth or design intensive is going on, you're definitely going to revise your design many times. FPGA's are massively on the rise (although slightly less so than Xilinx would like), and…
What's the tooling like for a typical, production-quality FPGA project nowadays? Last I checked, which is admittedly a couple of years ago (and I didn't dive in very deeply), it was a horrible mix of badly programmed vendor-specific Windows-only GUI tools. It seemed a lot like the embedded processor market where every single vendor has their own lock-in strategy and the whole ecosystem suffers for it. Has this improved in the meantime?
Re: FPGAs becoming more SoC-like
#5Earlier quoted context omitted.
It wasn't a question. ASIC isn't the tool for large volume, it's the tool for when you can accept a several year turnaround time for revisions, vs. a day or two. ASIC > FPGA... except if your design changes, ever. If anything high-bandwidth or design intensive is going on, you're definitely going to revise your design many times. FPGA's are massively on the rise (although slightly less so than Xilinx would like), and…
What's the tooling like for a typical, production-quality FPGA project nowadays? Last I checked, which is admittedly a couple of years ago (and I didn't dive in very deeply), it was a horrible mix of badly programmed vendor-specific Windows-only GUI tools. It seemed a lot like the embedded processor market where every single vendor has their own lock-in strategy and the whole ecosystem suffers for it. Has this improv…
The colleagues are telling me, that this ugly GUI works nowadays under Linux too. You also can script much using tcl commands. I have it running on Windows and it works somehow, but I am not happy user:-/
Re: FPGAs becoming more SoC-like
#6Earlier quoted context omitted.
It wasn't a question. ASIC isn't the tool for large volume, it's the tool for when you can accept a several year turnaround time for revisions, vs. a day or two. ASIC > FPGA... except if your design changes, ever. If anything high-bandwidth or design intensive is going on, you're definitely going to revise your design many times. FPGA's are massively on the rise (although slightly less so than Xilinx would like), and…
What's the tooling like for a typical, production-quality FPGA project nowadays? Last I checked, which is admittedly a couple of years ago (and I didn't dive in very deeply), it was a horrible mix of badly programmed vendor-specific Windows-only GUI tools. It seemed a lot like the embedded processor market where every single vendor has their own lock-in strategy and the whole ecosystem suffers for it. Has this improv…
It's still like that. It's an extremely conservative industry.
Re: FPGAs becoming more SoC-like
#7Earlier quoted context omitted.
It wasn't a question. ASIC isn't the tool for large volume, it's the tool for when you can accept a several year turnaround time for revisions, vs. a day or two. ASIC > FPGA... except if your design changes, ever. If anything high-bandwidth or design intensive is going on, you're definitely going to revise your design many times. FPGA's are massively on the rise (although slightly less so than Xilinx would like), and…
What's the tooling like for a typical, production-quality FPGA project nowadays? Last I checked, which is admittedly a couple of years ago (and I didn't dive in very deeply), it was a horrible mix of badly programmed vendor-specific Windows-only GUI tools. It seemed a lot like the embedded processor market where every single vendor has their own lock-in strategy and the whole ecosystem suffers for it. Has this improv…
Tooling is cheaper and more reliable at least.
Honestly I find the situation better than 20 years ago now on the embedded processor front. The worst thing we have now is broken shitty standard libs and compilers. You can dodge around those by picking assembly (PIC for example, mpasm is actually ok) or platforms with GCC implementations (ARM/AVR)
Re: FPGAs becoming more SoC-like
#8Earlier quoted context omitted.
It wasn't a question. ASIC isn't the tool for large volume, it's the tool for when you can accept a several year turnaround time for revisions, vs. a day or two. ASIC > FPGA... except if your design changes, ever. If anything high-bandwidth or design intensive is going on, you're definitely going to revise your design many times. FPGA's are massively on the rise (although slightly less so than Xilinx would like), and…
What's the tooling like for a typical, production-quality FPGA project nowadays? Last I checked, which is admittedly a couple of years ago (and I didn't dive in very deeply), it was a horrible mix of badly programmed vendor-specific Windows-only GUI tools. It seemed a lot like the embedded processor market where every single vendor has their own lock-in strategy and the whole ecosystem suffers for it. Has this improv…
Windows only tools? You must have been using Altera options (I briefly maintained the page for Quartus compatibility at wine, circa 2004). Even them have had Linux support for a while, Xilinx has Linux support for as far as I remember, at least some ten years.
The ecosystem is terrible, I agree with you. However, the lock in is restricted for the final synthesis part. Simulation is mostly done with (very expensive) third party tools, such as Mentor Graphics Modelsim, and in professional settings the build is automated to a point that opening the vendor's GUI is frowned upon.
There are some quality open sources tools on FPGA build automation, but most places I had contact with have their own internal tools.
Re: FPGAs becoming more SoC-like
#9Earlier quoted context omitted.
It wasn't a question. ASIC isn't the tool for large volume, it's the tool for when you can accept a several year turnaround time for revisions, vs. a day or two. ASIC > FPGA... except if your design changes, ever. If anything high-bandwidth or design intensive is going on, you're definitely going to revise your design many times. FPGA's are massively on the rise (although slightly less so than Xilinx would like), and…
What's the tooling like for a typical, production-quality FPGA project nowadays? Last I checked, which is admittedly a couple of years ago (and I didn't dive in very deeply), it was a horrible mix of badly programmed vendor-specific Windows-only GUI tools. It seemed a lot like the embedded processor market where every single vendor has their own lock-in strategy and the whole ecosystem suffers for it. Has this improv…
All the FPGA tools by Xilinx work well under Linux and Vivado is actually quite pleasant to use. Almost all of the EDA tools can be scripted with TCL (cadence has a host of other DSL aswell) so you don’t need to use the GUI if you don’t want to.
Re: FPGAs becoming more SoC-like
#10Earlier quoted context omitted.
What's the tooling like for a typical, production-quality FPGA project nowadays? Last I checked, which is admittedly a couple of years ago (and I didn't dive in very deeply), it was a horrible mix of badly programmed vendor-specific Windows-only GUI tools. It seemed a lot like the embedded processor market where every single vendor has their own lock-in strategy and the whole ecosystem suffers for it. Has this improv…
The colleagues are telling me, that this ugly GUI works nowadays under Linux too. You also can script much using tcl commands. I have it running on Windows and it works somehow, but I am not happy user:-/
Xilinx Vivado is not ugly; but resource heavy; so most people stick to tcl scripting.