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Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA, Shipping to Vendors

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Re: Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA, Shipping to Vendors

#11

Post by imbusy111 »

rjsw wrote: post #6
kev009 wrote: post #4

One stark flailure of the Altera acquisition is there has been little by way of tool chain integration. This is a CPU with a bag on the side, and that bag needs people that write HDL and understand computer architecture to make good use of. It's not really a harsh critique, but a warning that the lower you go is an increasingly smaller number and expensive lot of folks. Intel's marketing arm can't distort that realit…

Learning an HDL isn't that hard. I was productive within a few weeks of starting to use VHDL. A former colleague is now an Altera/Intel FAE, I will ask how things are going the next time we meet up for a beer.

How do you get into HDL and FPGAs? Seems like it will become a more and more important skill since all other avenues in performance improvement have come to a halt.

Re: Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA, Shipping to Vendors

#12

Post by duskwuff »

ktta wrote: post #9
kev009 wrote: post #4

One stark flailure of the Altera acquisition is there has been little by way of tool chain integration. This is a CPU with a bag on the side, and that bag needs people that write HDL and understand computer architecture to make good use of. It's not really a harsh critique, but a warning that the lower you go is an increasingly smaller number and expensive lot of folks. Intel's marketing arm can't distort that realit…

I wouldn't be surprised if Intel came up with tools which help make use of the FPGA using higher languages like C. Xilinx is already pushing it's Vivado HLx which is pretty much that. I'm not aware of Altera's current offerings but they won't overlook this so easily.

Intel/Altera has HLS tools as well:

https://www.altera.com/products/design-software/high-level-d...

Re: Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA, Shipping to Vendors

#13

Post by jsbto »

obl wrote: post #8
rjsw wrote: post #6

Earlier quoted context omitted.

Learning an HDL isn't that hard. I was productive within a few weeks of starting to use VHDL. A former colleague is now an Altera/Intel FAE, I will ask how things are going the next time we meet up for a beer.

HDLs are fine. I've found the tooling around them to be quite atrocious (slow, buggy, opaque, gui-based) though. Be it for synthesis, simulation, or even just compiler errors it's pretty bad compared to software.

Have to agree this is a major pain point for wider adoption. The current tools are mainly developed by a few big EDA vendors. I'm hoping, through the growth of open hardware communities, we'll start to see more friendly tools making progress.

Re: Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA, Shipping to Vendors

#14

Post by jsbto »

imbusy111 wrote: post #11
rjsw wrote: post #6

Earlier quoted context omitted.

Learning an HDL isn't that hard. I was productive within a few weeks of starting to use VHDL. A former colleague is now an Altera/Intel FAE, I will ask how things are going the next time we meet up for a beer.

How do you get into HDL and FPGAs? Seems like it will become a more and more important skill since all other avenues in performance improvement have come to a halt.

Could try something like Icarus Verilog for an open source compiler and start building some toy designs. There are some good communities and blogs to find help.

Re: Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA, Shipping to Vendors

#15

Post by slrz »

ktta wrote: post #9
kev009 wrote: post #4

One stark flailure of the Altera acquisition is there has been little by way of tool chain integration. This is a CPU with a bag on the side, and that bag needs people that write HDL and understand computer architecture to make good use of. It's not really a harsh critique, but a warning that the lower you go is an increasingly smaller number and expensive lot of folks. Intel's marketing arm can't distort that realit…

I wouldn't be surprised if Intel came up with tools which help make use of the FPGA using higher languages like C. Xilinx is already pushing it's Vivado HLx which is pretty much that. I'm not aware of Altera's current offerings but they won't overlook this so easily.

> I wouldn't be surprised if Intel came up with tools which help make use of the FPGA using higher languages like C.

These (almost by necessity) make you write code that doesn't look like any other C code. You can't just use some pre-existing C library and compile it to use FPGA resources. At that point, why not go a step further and just use a proper HDL?

Re: Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA, Shipping to Vendors

#16

Post by typon »

ktta wrote: post #9
kev009 wrote: post #4

One stark flailure of the Altera acquisition is there has been little by way of tool chain integration. This is a CPU with a bag on the side, and that bag needs people that write HDL and understand computer architecture to make good use of. It's not really a harsh critique, but a warning that the lower you go is an increasingly smaller number and expensive lot of folks. Intel's marketing arm can't distort that realit…

I wouldn't be surprised if Intel came up with tools which help make use of the FPGA using higher languages like C. Xilinx is already pushing it's Vivado HLx which is pretty much that. I'm not aware of Altera's current offerings but they won't overlook this so easily.

Altera/Intel has had OpenCL support for years now

Re: Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA, Shipping to Vendors

#17

Post by rwmj »

obl wrote: post #8
rjsw wrote: post #6

Earlier quoted context omitted.

Learning an HDL isn't that hard. I was productive within a few weeks of starting to use VHDL. A former colleague is now an Altera/Intel FAE, I will ask how things are going the next time we meet up for a beer.

HDLs are fine. I've found the tooling around them to be quite atrocious (slow, buggy, opaque, gui-based) though. Be it for synthesis, simulation, or even just compiler errors it's pretty bad compared to software.

Luckily there is (slow) progress on making good open source tools[1]. The Xilinx 7-series FPGAs were recently reverse-engineered too[2].

[1] https://rwmj.wordpress.com/2018/03/17/playing-with-picorv32-...

[2] https://github.com/SymbiFlow/prjxray

Re: Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA, Shipping to Vendors

#18

Post by analognoise »

sannee wrote: post #5
kev009 wrote: post #4

One stark flailure of the Altera acquisition is there has been little by way of tool chain integration. This is a CPU with a bag on the side, and that bag needs people that write HDL and understand computer architecture to make good use of. It's not really a harsh critique, but a warning that the lower you go is an increasingly smaller number and expensive lot of folks. Intel's marketing arm can't distort that realit…

> increasingly smaller number and expensive lot of folks. There is this sentiment on HN that people in EE/embedded space don't really get paid well (compared to the average Javascript-slinging frontend dev). Is this not true for HDL folks?

We get paid bank, there are very few of us, and the older you get and the more horror stories you've seen the more you're worth (unlike software). Gray in your beard is a feature, not a flaw.

You're responsible for time critical and/or DSP things that are critical system architecture, and will never be outsourced (it's key IP, you'd be stupid to outsource that).

Don't let anyone know, we have a good thing going on.

Re: Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA, Shipping to Vendors

#19

Post by aseipp »

ktta wrote: post #9
kev009 wrote: post #4

One stark flailure of the Altera acquisition is there has been little by way of tool chain integration. This is a CPU with a bag on the side, and that bag needs people that write HDL and understand computer architecture to make good use of. It's not really a harsh critique, but a warning that the lower you go is an increasingly smaller number and expensive lot of folks. Intel's marketing arm can't distort that realit…

I wouldn't be surprised if Intel came up with tools which help make use of the FPGA using higher languages like C. Xilinx is already pushing it's Vivado HLx which is pretty much that. I'm not aware of Altera's current offerings but they won't overlook this so easily.

Intel recently released their own High Level Synthesis compiler for Quartus; like HLx, it's free and you can use it now on whatever device you want. You still have to do the interconnection to the CPU, if you have one.

Unlike Xilinx, though, Intel (very very recently) just started offering their OpenCL-for-FPGA SDK for free, and it works on most of their device families, including Arria/Xeon and Cyclone/ARM. I always found it disappointing that the OpenCL SDKs were normally licensed, since they're more-or-less a logical extension of HLS support. So that's nice of Intel.

They don't have any equivalent to Xilinx SDSoC though, but for datacenter targets they're shipping a different set of SDKs anyway (called "OPAE"), so maybe in the future they'll build something on top of the OPAE and OpenCL support (e.g. single-source model, like Sycl)

Re: Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA, Shipping to Vendors

#20

Post by rjsw »

imbusy111 wrote: post #11
rjsw wrote: post #6

Earlier quoted context omitted.

Learning an HDL isn't that hard. I was productive within a few weeks of starting to use VHDL. A former colleague is now an Altera/Intel FAE, I will ask how things are going the next time we meet up for a beer.

How do you get into HDL and FPGAs? Seems like it will become a more and more important skill since all other avenues in performance improvement have come to a halt.

I just picked up a dev board and started making it flash LEDs, put patterns on the seven-segment display, then had a play with soft CPUs. This gave me ideas on how to use the technology in my job - embedded networking.

If you are coming from a software background then maybe look at getting a board with one of the ARM+FPGA hybrid chips, you can run a proper OS on the ARM CPU and I would guess that the bus interface to the FPGA part will be simpler than using Intel's UPI.

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