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Implementing FizzBuzz on an FPGA

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Re: Implementing FizzBuzz on an FPGA

#11

Post by q3k »

eebynight wrote: post #7
Cyph0n wrote: post #5

Earlier quoted context omitted.

The course focuses on synthesizable Verilog for FPGAs, so our instructor has made sure to clarify the upsides and downsides to using different logic for common tasks. Some interesting ones: * Never use asynchronous resets [on FPGAs] * if-else if-else chaining leads to unnecessary delays (priority encoders) * Avoid latches by making sure to assign default values * Never assume default values and/or states

Your professor seems great so far but pretty silly of him to teach you verilog instead of VHDL. As an EE myself I haven't seen a job description that says verilog over vhdl in a long time. Might want to familiarize yourself with both if you plan to pursue hardware design further.

Depends on where you're located. Counter anecdata: I've seen much more EE jobs asking for Verilog than VHDL :).

Re: Implementing FizzBuzz on an FPGA

#12

Post by duskwuff »

mrguyorama wrote: post #6

The most interesting part of all this is just how CHEAP some of the learning boards are. I don't know enough to understand how limited the ElbertV2 is, but at $30, it can still be pretty limited and a fun toy

> I don't know enough to understand how limited the ElbertV2 is...

The Spartan-3A (XC3S50A) is an older chip -- it's from 2007, and is itself a minor update to the 2003 Spartan-3 family -- and using it limits you to the Xilinx ISE toolchain, which hasn't been updated since 2014.

It's still a decent entry point to FPGA development, though.

Re: Implementing FizzBuzz on an FPGA

#13

Post by dzamlo »

eebynight wrote: post #7
Cyph0n wrote: post #5

Earlier quoted context omitted.

The course focuses on synthesizable Verilog for FPGAs, so our instructor has made sure to clarify the upsides and downsides to using different logic for common tasks. Some interesting ones: * Never use asynchronous resets [on FPGAs] * if-else if-else chaining leads to unnecessary delays (priority encoders) * Avoid latches by making sure to assign default values * Never assume default values and/or states

Your professor seems great so far but pretty silly of him to teach you verilog instead of VHDL. As an EE myself I haven't seen a job description that says verilog over vhdl in a long time. Might want to familiarize yourself with both if you plan to pursue hardware design further.

From what I read, this is very different between the US and Europe.

Re: Implementing FizzBuzz on an FPGA

#14

Post by gh02t »

leggomylibro wrote: post #8
mrguyorama wrote: post #6

The most interesting part of all this is just how CHEAP some of the learning boards are. I don't know enough to understand how limited the ElbertV2 is, but at $30, it can still be pretty limited and a fun toy

I got a couple of ICESticks I've been meaning to play with a little while ago, they're only $25 MSRP and have a 'USB stick' form factor. But it's hard to find and get started with a good open source toolchain. I have heard good things about IceStorm, but haven't gotten around to setting it up. It's great and inspiring to see people successfully stepping through these sorts of starter projects and documenting them, th…

> But it's hard to find and get started with a good open source toolchain

That's because there aren't any. The one you have happens to be the exception - it's the only FPGA line with an open source toolchain AFAIK. FPGAs are the realm of large, heavily proprietary build environments.

Re: Implementing FizzBuzz on an FPGA

#16

Post by TomVDB »

Cyph0n wrote: post #5
InitialLastName wrote: post #3

Earlier quoted context omitted.

I would suggest that you be VERY careful with that expressiveness if you want to do anything in an actual hardware context. Verilog makes it very easy (IME much easier than VHDL) to create structures that, while technically possible to synthesize, take enormous amounts of logic resources.

The course focuses on synthesizable Verilog for FPGAs, so our instructor has made sure to clarify the upsides and downsides to using different logic for common tasks. Some interesting ones: * Never use asynchronous resets [on FPGAs] * if-else if-else chaining leads to unnecessary delays (priority encoders) * Avoid latches by making sure to assign default values * Never assume default values and/or states

* Never use asynchronous resets [on FPGAs]

It makes no difference for most FPGAs. Most have dedicated resources dedicated to resets and consume equal resources for async and sync resets.

For ASIC, sync resets these days are considered safer against glitches because they only have an impact during a rising edge of the clock instead of all the time.

But it's not something to be super religious about.

Re: Implementing FizzBuzz on an FPGA

#17

Post by TomVDB »

eebynight wrote: post #7
Cyph0n wrote: post #5

Earlier quoted context omitted.

The course focuses on synthesizable Verilog for FPGAs, so our instructor has made sure to clarify the upsides and downsides to using different logic for common tasks. Some interesting ones: * Never use asynchronous resets [on FPGAs] * if-else if-else chaining leads to unnecessary delays (priority encoders) * Avoid latches by making sure to assign default values * Never assume default values and/or states

Your professor seems great so far but pretty silly of him to teach you verilog instead of VHDL. As an EE myself I haven't seen a job description that says verilog over vhdl in a long time. Might want to familiarize yourself with both if you plan to pursue hardware design further.

VHDL is popular in Europe and the US East Coast. Verilog is king on the West Coast.

An an EE who was schooled in VHDL, gave VHDL classes to new hires and was conditioned to look down on Verilog: after moving from Europe to the East Coast and then the West Coast, I eventually saw the error of my ways and I'm very happy to not have to deal with VHDL anymore.

And for the open source crowd: there is a much large body of decent quality open source Verilog tools than there is for VHDL. So as a hobbyist, it's really a nobrainer.

Re: Implementing FizzBuzz on an FPGA

#18

Post by TomVDB »

For those looking for cheap FPGA boards, I highly recommend looking for something that is based on the Lattice ICE40. The cheapest board you can find is probably the $9 Upduino, though trickier to get going. (Complete lack of documentation.)

But there are tons of hobby boards in existence.

The best part is Project IceStorm, a fully open source tool flow, from synthesis to bitstream. While not the best in terms of optimization, it's killer feature is that it's blazing fast. You can get small design synthesized and converted to a place-and-routed bitstream in under a minute.

Re: Implementing FizzBuzz on an FPGA

#19

Post by TomVDB »

leggomylibro wrote: post #8
mrguyorama wrote: post #6

The most interesting part of all this is just how CHEAP some of the learning boards are. I don't know enough to understand how limited the ElbertV2 is, but at $30, it can still be pretty limited and a fun toy

I got a couple of ICESticks I've been meaning to play with a little while ago, they're only $25 MSRP and have a 'USB stick' form factor. But it's hard to find and get started with a good open source toolchain. I have heard good things about IceStorm, but haven't gotten around to setting it up. It's great and inspiring to see people successfully stepping through these sorts of starter projects and documenting them, th…

You really should try IceStorm. I've been using it for the past month. It works extremely well and it's fast.

Re: Implementing FizzBuzz on an FPGA

#20

Post by katastic »

TomVDB wrote: post #18

For those looking for cheap FPGA boards, I highly recommend looking for something that is based on the Lattice ICE40. The cheapest board you can find is probably the $9 Upduino, though trickier to get going. (Complete lack of documentation.) But there are tons of hobby boards in existence. The best part is Project IceStorm, a fully open source tool flow, from synthesis to bitstream. While not the best in terms of opt…

My problem (years ago) was that with Lattice, there just aren't as many tutorials/easy-EDA and they kind of expect you to know what you're doing.

So if you've never taken a class on FPGA's and learned how netlists work, et al, Lattice may be a harder time. I ended up buying a cheap Altera afterward just to learn.

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