Implementing FizzBuzz on an FPGA
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Implementing FizzBuzz on an FPGA
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Re: Implementing FizzBuzz on an FPGA
#2Great article! I've also been learning Verilog -- albeit in an academic setting -- and it has been an interesting experience. I discovered that you can do surprisingly complex things in Verilog (at least, from a digital logic point of view) using less code than I initially expected!
Re: Implementing FizzBuzz on an FPGA
#3Great article! I've also been learning Verilog -- albeit in an academic setting -- and it has been an interesting experience. I discovered that you can do surprisingly complex things in Verilog (at least, from a digital logic point of view) using less code than I initially expected!
I would suggest that you be VERY careful with that expressiveness if you want to do anything in an actual hardware context. Verilog makes it very easy (IME much easier than VHDL) to create structures that, while technically possible to synthesize, take enormous amounts of logic resources.
Re: Implementing FizzBuzz on an FPGA
#4Amazing project to learn how FPGAs work. Not overkill with some high speed interfaces, but touches all problems: no easy division by 3 and 5, counters everywhere, no copy/paste solutions, no libraries with helpful functions. Though Xilinx ISE is obsolete, Vivado is the current tool.
Re: Implementing FizzBuzz on an FPGA
#5Great article! I've also been learning Verilog -- albeit in an academic setting -- and it has been an interesting experience. I discovered that you can do surprisingly complex things in Verilog (at least, from a digital logic point of view) using less code than I initially expected!
I would suggest that you be VERY careful with that expressiveness if you want to do anything in an actual hardware context. Verilog makes it very easy (IME much easier than VHDL) to create structures that, while technically possible to synthesize, take enormous amounts of logic resources.
The course focuses on synthesizable Verilog for FPGAs, so our instructor has made sure to clarify the upsides and downsides to using different logic for common tasks.
Some interesting ones:
* Never use asynchronous resets [on FPGAs]
* if-else if-else chaining leads to unnecessary delays (priority encoders)
* Avoid latches by making sure to assign default values
* Never assume default values and/or states
Re: Implementing FizzBuzz on an FPGA
#6The most interesting part of all this is just how CHEAP some of the learning boards are. I don't know enough to understand how limited the ElbertV2 is, but at $30, it can still be pretty limited and a fun toy
Re: Implementing FizzBuzz on an FPGA
#7Earlier quoted context omitted.
I would suggest that you be VERY careful with that expressiveness if you want to do anything in an actual hardware context. Verilog makes it very easy (IME much easier than VHDL) to create structures that, while technically possible to synthesize, take enormous amounts of logic resources.
The course focuses on synthesizable Verilog for FPGAs, so our instructor has made sure to clarify the upsides and downsides to using different logic for common tasks. Some interesting ones: * Never use asynchronous resets [on FPGAs] * if-else if-else chaining leads to unnecessary delays (priority encoders) * Avoid latches by making sure to assign default values * Never assume default values and/or states
Your professor seems great so far but pretty silly of him to teach you verilog instead of VHDL. As an EE myself I haven't seen a job description that says verilog over vhdl in a long time. Might want to familiarize yourself with both if you plan to pursue hardware design further.
Re: Implementing FizzBuzz on an FPGA
#8The most interesting part of all this is just how CHEAP some of the learning boards are. I don't know enough to understand how limited the ElbertV2 is, but at $30, it can still be pretty limited and a fun toy
I got a couple of ICESticks I've been meaning to play with a little while ago, they're only $25 MSRP and have a 'USB stick' form factor.
But it's hard to find and get started with a good open source toolchain. I have heard good things about IceStorm, but haven't gotten around to setting it up.
It's great and inspiring to see people successfully stepping through these sorts of starter projects and documenting them, though!
Re: Implementing FizzBuzz on an FPGA
#9Amazing project to learn how FPGAs work. Not overkill with some high speed interfaces, but touches all problems: no easy division by 3 and 5, counters everywhere, no copy/paste solutions, no libraries with helpful functions. Though Xilinx ISE is obsolete, Vivado is the current tool.
Unfortunately Vivado doesn't support the Spartan 6 chip used by the Mojo board, just Spartan 7 and later.
Re: Implementing FizzBuzz on an FPGA
#10> While this may look like code in a normal programming language, it operates entirely differently.
So happy to see this called out up-front. One of the hardest things with FPGAs as a developer is understanding that you're reconfiguring hardware instead of a series of serial asm/opcodes. They look superficially the same but have very different requirements and constraints under the hood.