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Western Digital Plans to Ship More Than One Billion RISC-V Cores a Year

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Re: Western Digital Plans to Ship More Than One Billion RISC-V Cores a Year

#131

Post by kogepathic »

userbinator wrote: post #103
jstewartmobile wrote: post #23

I guess this will be nice for industry, which may pass the savings along to the consumer, but as far as having auditable hardware that you have some control over, I don't see how this is any better than the ARM SoCs we already have--unless you're going to roll your own system on an FPGA. That, and I'm kind of disappointed everyone has drunk the RISC kool-aid. I think a lot of RISC "performance" has more to do with co…

That, and I'm kind of disappointed everyone has drunk the RISC kool-aid. Agree completely. One only has to look at the prominence (or lack thereof) of MIPS, the other "pure RISC" architecture, to see that it's not known for being anything other than cheap. Plenty of low-end Chinese routers, phones, tablets, and various Android-running devices use MIPS; and their performance (or once again, lack thereof) is notable. A…

> Plenty of low-end Chinese routers, phones, tablets, and various Android-running devices use MIPS

I don't think MIPS is common in phones or tablets anymore, those have moved on to the low end of ARM.

However, MIPS is still used in many networking devices and was up until recently, also used in set-top boxes (STB) like the kind you get from your cable provider.

> their performance (or once again, lack thereof) is notable

You don't need gobs of CPU performance in networking devices. All the layer 2 packet handling is done in hardware, and for layer 3 routing the MIPS core(s) are powerful enough to offer 100Mbit NAT performance, which is 99% of what home internet users need currently.

Most managed switches today are either using an updated version of the PowerPC 630 or some ancient and low clocked ARM core. [1]

You don't need gigahertz CPUs in these devices because the CPU is only there to run the management OS (typically Linux) which then configures the switching/routing hardware.

> One only has to look at the prominence (or lack thereof) of MIPS

There are billions of MIPS devices out there. Most homes will have one in their WiFi router, and others in their STB. The only reason MIPS isn't "prominent" is because the products aren't advertised as containing a MIPS core, and people don't know it's MIPS.

[1] https://h50146.www5.hpe.com/products/networking/datasheet/4A...

Re: Western Digital Plans to Ship More Than One Billion RISC-V Cores a Year

#132

Post by jstewartmobile »

jabl wrote: post #118
jstewartmobile wrote: post #23

I guess this will be nice for industry, which may pass the savings along to the consumer, but as far as having auditable hardware that you have some control over, I don't see how this is any better than the ARM SoCs we already have--unless you're going to roll your own system on an FPGA. That, and I'm kind of disappointed everyone has drunk the RISC kool-aid. I think a lot of RISC "performance" has more to do with co…

> That, and I'm kind of disappointed everyone has drunk the RISC kool-aid. Well, the thing is, RISC "won" the "RISC vs. CISC" wars, in the sense that more or less every ISA designed since has been RISC [1]. Of course, CISC also won in the sense that x86 is still around, and Intel is of course fabulously successful. So at least for high-end cores designed with a big budget, the extra decoder complexity doesn't appear…

Like you said ARM and x86, RISC and CISC, are the winners. I just wonder how much of that victory is due to circumstances of the time (like weak late-1980s compilers) and how much was due to clear technical superiority.

Re: Western Digital Plans to Ship More Than One Billion RISC-V Cores a Year

#133

Post by microcolonel »

hawski wrote: post #121
microcolonel wrote: post #38

Earlier quoted context omitted.

> Out of the whole RISC-V ecosystem it looks like only SiFive is working on that, so it will take time. If you look at Qualcomm's strategy with x86 competition (using Dynamic Binary Translation), it's not hard to imagine that they might consider building RISC-V application processors; especially once they've proven their ability to deliver enough compatibility and performance with DBT to compete on ISAs for which the…

Can Qualcomm do that? Tegra K1 from nVidia was supposed to be x86 in similar way. They couldn't get a license so it became an ARM core.

> Can Qualcomm do that? Tegra K1 from nVidia was supposed to be x86 in similar way. They couldn't get a license so it became an ARM core.

NVIDIA bought Transmeta; Transmeta basically proved (by being sued into insolvency) that they couldn't compete on (up to date, still under patent) x86 with hardware or whole-system software DBT for licensing reasons. NVIDIA's K1/Denver products are very similar to Transmeta architectures still, but for ARMv8 instead of x86(or, more interesting, AMD64), and in this case they have an architectural license.

What Qualcomm is doing is different. Qualcomm is doing software-only Dynamic Binary Translation, and they're doing it on a per-application basis (similar to the Mac 68K emulator, Rosetta, WOW64, or QEMU user mode).

Re: Western Digital Plans to Ship More Than One Billion RISC-V Cores a Year

#134

Post by krylon »

runeks wrote: post #129
windlessstorm wrote: post #128

Earlier quoted context omitted.

Tiny microprocessors are there in almost all devices supporting DMA since long time right? So what this RISC-V versions will bring new to the table?

> So what this RISC-V versions will bring new to the table? Not much, except being open, so WD can produce them without paying anyone royalties.

But in that case there would not be much of a point in making such an announcement, right? From a user perspective, I do not care at all what ISA the microcontroller inside the HDD/SSD uses, if it is not user accessible.

Unless they pass the savings on to their customers, that is. And even then, I am not so sure. Shaving a couple of cents of the price of a disk drive does not seem like a big deal to me.

Their stockholders might care, though.

Re: Western Digital Plans to Ship More Than One Billion RISC-V Cores a Year

#135

Post by microcolonel »

mrweasel wrote: post #123
microcolonel wrote: post #3

I think the level of industry enthusiasm for RISC-V is so palpable, in part, because the messaging from day one has been unequivocally: RISC-V will be the standard ISA for every form factor, in every market. Can't wait to put a RISC-V SBC in my ThinkPad X220 chassis. :- )

Sadly I doubt that anyone will make RISC-V motherboard with PCIe slots, or in any other way supply hardware that will make it easy to build a RISC-V workstation. We aren't seeing any ARM workstations and PowerPC boards aren't exactly affordable. The market for these processors aren't workstation or laptop, there simply aren't enough of us willing to buy them.

> Sadly I doubt that anyone will make RISC-V motherboard with PCIe slots

The SiFive Freedom U500 platform (already available to integrators, AFAIK) has a PCIe 3.0 bus, it would be natural to have a PCIe slot (or a couple, if they have the lanes for it) on the dev board.

Re: Western Digital Plans to Ship More Than One Billion RISC-V Cores a Year

#136

Post by jstewartmobile »

adrianN wrote: post #126
jstewartmobile wrote: post #23

I guess this will be nice for industry, which may pass the savings along to the consumer, but as far as having auditable hardware that you have some control over, I don't see how this is any better than the ARM SoCs we already have--unless you're going to roll your own system on an FPGA. That, and I'm kind of disappointed everyone has drunk the RISC kool-aid. I think a lot of RISC "performance" has more to do with co…

I believe the "we just need a better compiler" thing has been tried with e.g. Itanium and turned out to be harder than expected.

Itanium had many things that needed sorting, and it would have taken one hell of a compiler to sort it all.

The RISC "victory" was called in the early 90s, and it was mostly benchmarked off of late 1980s compilers that were targeted to least-common-denominator register machines, so most fancy CISC instructions were never emitted, and stack architectures were barely even a consideration.

Even on RISC-to-RISC comparisons, having a compiler that caters to your specific ISA makes a huge difference. So, if it was a victory, I wouldn't call it a clear one.

Re: Western Digital Plans to Ship More Than One Billion RISC-V Cores a Year

#137

Post by frik »

csense wrote: post #28

From the headline, I would guess WD is putting a user accessible CPU in each of their disk drives, idea being that if you have a CPU living close to the drive, then e.g. map+reduce workloads can be more efficiently executed. Instead of going with ARM or Intel, I guess the CPU's are using some less famous architecture called RISC-V. Then I read the article, and the article is so full of buzzwords and genericisms that…

If RISC-V turns out a competitor to ARM based Raspberry PI than it would be great.

If this initiative turns out to be a smart hard disk (HDD) that runs yet another full CPU with Minix like the infamous Intel ME gate. Then we don't need it, the world needs not another spy device, aka insecure hardware that has full acccess, yet is invisible to the users (= owner) of the device.

Re: Western Digital Plans to Ship More Than One Billion RISC-V Cores a Year

#138

Post by _jal »

krylon wrote: post #134
runeks wrote: post #129

Earlier quoted context omitted.

> So what this RISC-V versions will bring new to the table? Not much, except being open, so WD can produce them without paying anyone royalties.

But in that case there would not be much of a point in making such an announcement, right? From a user perspective, I do not care at all what ISA the microcontroller inside the HDD/SSD uses, if it is not user accessible. Unless they pass the savings on to their customers, that is. And even then, I am not so sure. Shaving a couple of cents of the price of a disk drive does not seem like a big deal to me. Their stockho…

Depends on what you care about, I suppose. I find it interesting, because I am interested in low-power processors.

This move, if it works well for WD, could lead to more attention being paid to a more open competitor to ARM, which would provide some competition and put downward pressure on ARM pricing. That, in turn, could have some potentially interesting second-order effects.

But yeah, if you only care about consumer prices and visible features, this is probably pretty boring stuff.

Re: Western Digital Plans to Ship More Than One Billion RISC-V Cores a Year

#139

Post by krylon »

_jal wrote: post #138
krylon wrote: post #134

Earlier quoted context omitted.

But in that case there would not be much of a point in making such an announcement, right? From a user perspective, I do not care at all what ISA the microcontroller inside the HDD/SSD uses, if it is not user accessible. Unless they pass the savings on to their customers, that is. And even then, I am not so sure. Shaving a couple of cents of the price of a disk drive does not seem like a big deal to me. Their stockho…

Depends on what you care about, I suppose. I find it interesting, because I am interested in low-power processors. This move, if it works well for WD, could lead to more attention being paid to a more open competitor to ARM, which would provide some competition and put downward pressure on ARM pricing. That, in turn, could have some potentially interesting second-order effects. But yeah, if you only care about consum…

Mmmmh, now that I think of it: Does WD have their own fabs, or do they buy their chips from other vendors.

And if it's the latter - would WD buying a couple of billion chips a year have any effect on prices?

And now that you mention it - a company like WD announcing they will use RISC-V in their disks means they are serious about this, which in turn might make it easier for other to consider RISC-V a serious option.

I am very excited about RISC-V in theory, but unless somebody builds a "Raspberry-V", so to speak, it will probably be a long time before I get to play with one of these. I also think a high-performance implementation of RISC-V could make for an attractive component of a desktop machine / workstation. The Talos Raptor / II seems to be a sweet machine, but it is totally outside my budget. A less-high-end machine built around a RISC-V might change the equation.

Re: Western Digital Plans to Ship More Than One Billion RISC-V Cores a Year

#140

Post by CyberDildonics »

jstewartmobile wrote: post #136
adrianN wrote: post #126

Earlier quoted context omitted.

I believe the "we just need a better compiler" thing has been tried with e.g. Itanium and turned out to be harder than expected.

Itanium had many things that needed sorting, and it would have taken one hell of a compiler to sort it all. The RISC "victory" was called in the early 90s, and it was mostly benchmarked off of late 1980s compilers that were targeted to least-common-denominator register machines, so most fancy CISC instructions were never emitted, and stack architectures were barely even a consideration. Even on RISC-to-RISC compariso…

I think anyone who tries to do a different architecture will have to put forward huge R+D themselves for proper code generation. Likely in the form of an LLVM backend, webasm JIT, maybe JVM, as well as on chip hardware techniques that at least fill the same role as OO execution.

I can't think of any hardware architecture that focused on super efficient execution and let the instruction generation chips fall where they may. Maybe the Cell in the PS3. Every other successful chip has seemed to try to deal with whatever instructions it is given as best it can.

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