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Open-source chip RISC-V to take on closed x86, ARM CPUs

computerworld.com.au

91–100 of 157 posts

Re: Open-source chip RISC-V to take on closed x86, ARM CPUs

#91
post #71

Earlier quoted context omitted.

Well, a 10 million dollar license is nothing of you factor the Fab costs

Apples and oranges. The companies that design the chips and pays royalties for IP are mostly fabless (with rare exceptions like Intel). The fabs are owned by separate entities like TSMC, Samsung, SMIC that specialize in the production itself. The fabs don't pay for CPU IP (they sometimes pay for some other basic IP to be able to offer them as standard to their customers, but that doesn't cover CPUs/GPUs). About Samsu…

The older OpenRISC had already found a few niches. For example, the management core in some of Allwinner's newer ARM SoCs is apparently OpenRISC, presumably because they didn't want to license another lower-end ARM core or something. Similarly, some Samsung TVs apparently use it.

Re: Open-source chip RISC-V to take on closed x86, ARM CPUs

#92
post #90

AFAIK, most advanced RISC-V design includes superscalar and OoOE (e.g. comparable to a MIPS R10000 (1995) or an Intel Pentium Pro (1995)), while the RISC-V for the IoT is comparable to a typical single instructions per clock RISC CPU, e.g. MIPS R3000 (1988). The success in the IoT will depend not only in a cheaper price because of no royalties, but also in the "ecosystem": peripherals, buses, etc. Running Linux is a…

Nvidia would be perfect

Re: Open-source chip RISC-V to take on closed x86, ARM CPUs

#93

Earlier quoted context omitted.

Atm, arm is likely a better fit for that.

I wish ARM made all their manufactures use UEFI. Microsoft did for their phones, but the bootloaders are locked. All the other ARM devices are SoCs with random shit connected to random pins and non-upstreamable kernels. It's not a platform. For a new design to work, it really need to be a sold platform, with a spec and kernels that don't need per-device images to boot and run. Device trees help, but they're just not…

> SoCs with random shit connected to random pins and non-upstreamable kernels

The non-upstreamable part is due to variety factors, including but not limited to dubious code quality, tendency to reinvent things in house and unwillingness to share code with competitors and develop common frameworks. UEFI won't help with these particular issues.

As for random shit connected to random GPIOs (or mapped to random memory), you probably really want ACPI. Fwiw, ACPI is said to be coming to ARM and last time I heard Linux developers weren't exactly excited - ACPI means running opaque vendor-provided bytecode which pokes I/O registers behind the OS's back and, if x86 is anything to go by, contains countless bugs which can't be fixed without the vendor releasing firmware update and users applying it, so you end up with a collection of machine-specific workarounds anyway.

Re: Open-source chip RISC-V to take on closed x86, ARM CPUs

#94
post #93

Earlier quoted context omitted.

I wish ARM made all their manufactures use UEFI. Microsoft did for their phones, but the bootloaders are locked. All the other ARM devices are SoCs with random shit connected to random pins and non-upstreamable kernels. It's not a platform. For a new design to work, it really need to be a sold platform, with a spec and kernels that don't need per-device images to boot and run. Device trees help, but they're just not…

> SoCs with random shit connected to random pins and non-upstreamable kernels The non-upstreamable part is due to variety factors, including but not limited to dubious code quality, tendency to reinvent things in house and unwillingness to share code with competitors and develop common frameworks. UEFI won't help with these particular issues. As for random shit connected to random GPIOs (or mapped to random memory),…

devicetree is how this is all typically managed for Linux on ARM.

Re: Open-source chip RISC-V to take on closed x86, ARM CPUs

#95
post #78

After enjoying coding on 680x0 in my youth and later being frustrated by x86, I acclaim that new ISA. There is a design decision I'm curious about but I could not find related information. How did they come with the names "x0, x1, x2..." for general purpose registers, instead of the more conventional "r0, r1, r2..."?

x for "fixed point". r for "register" is too vague.

Re: Open-source chip RISC-V to take on closed x86, ARM CPUs

#96
post #92
post #90

AFAIK, most advanced RISC-V design includes superscalar and OoOE (e.g. comparable to a MIPS R10000 (1995) or an Intel Pentium Pro (1995)), while the RISC-V for the IoT is comparable to a typical single instructions per clock RISC CPU, e.g. MIPS R3000 (1988). The success in the IoT will depend not only in a cheaper price because of no royalties, but also in the "ecosystem": peripherals, buses, etc. Running Linux is a…

Nvidia would be perfect

NVidia is busy with their own ARM designs.

Re: Open-source chip RISC-V to take on closed x86, ARM CPUs

#97
post #53

RISC-V is atleast 10 years away from competing with x86 and ARM. It is just now getting to a point where it can power arduino class hardware. Long way to go... but looks promising.

The Freedom E310 chip in the HiFive1 board is shipping today and is already competitive with embedded ARM: https://www.crowdsupply.com/sifive/hifive1/#comparisons . It's comically faster (i.e., 100x) than the AVR chip in the Arduino Uno board, but the similar form factor makes it cheap & easy for early adopters to play around with. I'd bet that within five years a good proportion, even the majority, of Amazon & Googl…

Is there a power consumption comparison?

Re: Open-source chip RISC-V to take on closed x86, ARM CPUs

#98
post #53

Earlier quoted context omitted.

The Freedom E310 chip in the HiFive1 board is shipping today and is already competitive with embedded ARM: https://www.crowdsupply.com/sifive/hifive1/#comparisons . It's comically faster (i.e., 100x) than the AVR chip in the Arduino Uno board, but the similar form factor makes it cheap & easy for early adopters to play around with. I'd bet that within five years a good proportion, even the majority, of Amazon & Googl…

Is there a power consumption comparison?

(I know there is DMIPS/mW, but looking for a direct power consumption comparison)

Re: Open-source chip RISC-V to take on closed x86, ARM CPUs

#99
post #84

I thought that microprocessor production and design was fraught with risk of infringing on other designers' patents (even for original ISAs). I can see that industry heavyweights have arrived to support RISC-V, so hopefully that comes with a team of professors/lawyers that could defend them. But, why now? Why couldn't this have happened sooner? Didn't Sun try to create an open SPARC processor design? What does RISC-V…

> does anyone expect RISC-V to really go head-to-head with Xeon, Opteron, ThunderX, Centriq? Yes, and no. RISC-V is disruptive [1] to both ARM and x86. But before it can run (compete with Intel CPUs), it needs to crawl (compete with low-end ARM CPUs/microcontrollers). It could take a decade or more before RISC-V competes at the high-end. Basically think of it as following ARM's path but on a much more accelerated pat…

I think part of the accelerated path will be that we are reaching the limits of 'easy' (in the billions already) process improvements.

When everyone and his dog has 14nm you can't rely on process to keep you ahead, Ryzen has shown this partially recently, Broadwell level IPC on an Octacore processor for less than Intel sells a Quad core.

It's going to be a bloodbath as the middle eats into the top.

Re: Open-source chip RISC-V to take on closed x86, ARM CPUs

#100
post #80
post #74

Earlier quoted context omitted.

You're right, but key words here are "At this date". What you said could have been said exactly in the same way about Linux against commercial Unices about 15 years ago. It's a long game here, and we're only in the early phase. And it may not take that long, but we'll see. Regarding technology, just as Linux initially the key is not having a technological advantage, but being cheaper and good enough. The improvements…

RISC-V is thrown around like if it's an already working CPU but it is not. It is just a document describing an ISA, you can't compare it to Linux, it's a completely different thing. There are a lot of costs in implementing an ISA and that includes: design, functional verification, physical implementation and software testing. All those steps together will require hundreds and hundreds of engineers, many expensive too…

When I did a presentation on RISC-V last year I counted 6 real implementations (full custom ASICs). Now granted only one or two of those you can buy, the others are research projects, but they do exist and they did produce real silicon. This year we should see a couple of 64 bit implementations, which is when it'll get really interesting.

There are of course multiple FPGA implementations (I have one about 2 feet away from me now), but they are very slow.

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