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Intel Shows 2.5D FPGA at ISSCC

eetimes.com

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Re: Intel Shows 2.5D FPGA at ISSCC

#91

Was this headline changed? I thought it referenced AMD originally?

Yes, it originally linked to the second page of this article, which is subtitled "Zen squeezes x86 area and power" and has a completely different topic. The HN submission received the editorialized title "AMD Zen core is 10% smaller than Intel's current gen, and has 2x larger L2" which is why the top comment (https://news.ycombinator.com/item?id=13642442) references AMD as the focus of the article.

Like EETimes articles (and to be fair, they're not alone in the practice), this article is basically just a collation of manufacturer press releases.

To hammer this point home, or perhaps to reach a 500 word target, the author concludes by discussing a new Mediatek mobile SOC completely unrelated to either Intel's FPGAs on page 1 or the AMD Zen cores on the top half of page 2.

Re: Intel Shows 2.5D FPGA at ISSCC

#92
post #32

Earlier quoted context omitted.

I think that's why so many people go with the older HP microservers. Super cheap, nice form factor, just add ECC RAM and HDDs.

I have an HP MicroServer N40L that I bought several years ago, and it's almost a doorstop now. Its CPU (dual-core 1.5 GHz AMD Turion II Neo) is slow and doesn't support AES-NI. It maxes out at 8 GB of RAM (16 GB of RAM if the stars align and it likes the RAM you bought). It has one GigE port, and SATA ports are limited to 3 Gbps (SATA II). Expansion is limited to an eSATA port, USB 2.0 ports, a low-profile PCIe 2.0 x…

Underpowered? With that much hardware I could run 32 Q3 and UT99 servers at once without blinking.

Re: Intel Shows 2.5D FPGA at ISSCC

#93
I'm slightly confused why everyone's talking about CPUs and ignoring the FPGA!

Anyway, it's an interesting technique. An extension of chip-on-module packaging where instead of having a circuit board made of FR4 you have a tiny PCB made of multilayer silicon. This allows fast connections between chips made with different processes (CPU/DRAM/Flash are somewhat incompatible), and joining small chips together into large ones to improve yield.

Re: Intel Shows 2.5D FPGA at ISSCC

#94

Getting a bit bored of leaks, press releases and even specs. The proof of a CPU is in how it benchmarks across real workloads. We're 2-3 weeks away from global release. People buying components NOW are exactly the sort of people AMD should be working their socks off to stop buying Intel parts. But instead of any firm performance figures, we have rumour. The only reason I can imagine AMD is still keeping the press und…

"The proof of a CPU is in how it benchmarks across real workloads." Define 'real workload' here. Are we talking about a workload where the compiler specifically optimizes for Intel, or where the executable chooses unoptimized paths if it finds anything other than intel processors inside? Because I've found that when it comes to raw x86, no SSE anything or other nonsense; pure, unadulterated original x86, AMD simply o…

Because I've found that when it comes to raw x86, no SSE anything or other nonsense; pure, unadulterated original x86, AMD simply owns.

Who cares, though? Is that something that matters?

Re: Intel Shows 2.5D FPGA at ISSCC

#95
post #2

Link seems to go to " Intel Shows 2.5D FPGA at ISSCC " instead? edit: oh, derp. nevermind. there's a second page: http://www.eetimes.com/document.asp?doc_id=1331317&page_numb... edit edit: so apparently page 2 can't be linked to. whatever. bottom of the article content has a "next page" link.

Your link takes me to page 2. Running Chrome with uBlock Origin; not sure why you're being redirected to page 1.

Re: Intel Shows 2.5D FPGA at ISSCC

#96
post #66

Earlier quoted context omitted.

I strongly doubt AMD are specifically targeting the desktop/laptop CPU market. * Cloud computing has an absurd market cap.[1] * Ryzen has some features that specifically target cloud computing: * * More PCIe lanes than a Xeon. These are basically useless for desktop/gaming (as SLI doesn't scale beyond 2 cards). This shines for cloud computing because you can fit more GPUs in a blade. There's also ML to consider. * *…

"SLI doesn't scale beyond 2 cards" Guess you weren't around in the days of Quad VooDoo 2 GPU rigs. They most certainly did scale. nVidia and AMD's implementation? Nope. They screwed the pooch with that one and will never recover until they learn that the older way was indeed better.

SLI only matters for gaming - which is outside of the scope of my argument. Regardless, it looks like 3Dfx SLI wasn't that great[1] and I did own a Diamond Monster 3D II.

[1]: http://www.tomshardware.com/reviews/diamond-monster-3d-ii,52...

Re: Intel Shows 2.5D FPGA at ISSCC

#97
post #63

Earlier quoted context omitted.

> they struggled to meet demand and manufacture enough chips. I would think, and hope, that the situation is better now. Back then, AMD was manufacturing their chips in house, now they're manufactured by GlobalFoundries and TSMC.

GlobalFoundries was spin off from the AMD fabrication units so I don't think they got an immediate advantage with them. Regardless of that AMD is a much smaller company than Intel (~9k employees vs ~100k employees) so it is quite a remarkable feat that they have managed to stay in the competition for so long.

I speculate that they could have been extinguished years ago by intel, if it weren't for their fears of anti-competition and monopoly.

Either way, I predict both will slowly be eaten by GPU-driven processing and ARM desktops. It's going to be a very tough secular cycle for CISC chip makers in the coming decade.

Re: Intel Shows 2.5D FPGA at ISSCC

#98
post #93

I'm slightly confused why everyone's talking about CPUs and ignoring the FPGA! Anyway, it's an interesting technique. An extension of chip-on-module packaging where instead of having a circuit board made of FR4 you have a tiny PCB made of multilayer silicon. This allows fast connections between chips made with different processes (CPU/DRAM/Flash are somewhat incompatible), and joining small chips together into large…

Seems like the title was changed from last night. It was about how AMD's new processors took 10% less die space than intel chips

Re: Intel Shows 2.5D FPGA at ISSCC

#99
post #93

I'm slightly confused why everyone's talking about CPUs and ignoring the FPGA! Anyway, it's an interesting technique. An extension of chip-on-module packaging where instead of having a circuit board made of FR4 you have a tiny PCB made of multilayer silicon. This allows fast connections between chips made with different processes (CPU/DRAM/Flash are somewhat incompatible), and joining small chips together into large…

Can you ELI5 how putting an FPGA on a cisc die will ultimately improve performance? Does it affect both multi core and single core benchmarks?

Re: Intel Shows 2.5D FPGA at ISSCC

#100
post #64
post #39

Earlier quoted context omitted.

> AMD said its upcoming Zen x86 core fits into a 10 percent smaller die area than Intel’s currently shipping second-generation 14nm processor. Sounds totally irrelevant.

It's actually super-relevant. Here's what this means. Intel has about 10% advantage in process technology. Yet despite that, AMD's chip is still 10% smaller than Intel's chip. That gives AMD an effective 20% architectural advantage over Intel for similar performance. This is why Intel is now scrambling to "streamline" its architecture as soon as possible (but won't be able to do it for the next 3 years or so). A smal…

>Here's what this means. Intel has about 10% advantage in process technology. Yet despite that, AMD's chip is still 10% smaller than Intel's chip. That gives AMD an effective 20% architectural advantage over Intel for similar performance.

No, the conclusion you should be drawing is "AMD is using ~20% less transistors per core. What did AMD not implement that Intel did and how badly does that hurt Ryzen's performance?"

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