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pbsd

HN member
Joined
Mon, Nov 14, 2011, 10:55 PM UTC
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2,770
Public activity
820 items

About pbsd

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Recent public activity

  1. comment
    Comment #49216260

    The cycle count for RDTSC is ~25 cycles on Skylake-era microarchitectures. The 49 number shown in the OP seems off.

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    Comment #47443830

    I mean, he's comparing 2024 Zen 5 and M4 against two generations behind 2022 Intel Raptor Lake. The Lion Cove should be roughly on par with the M4 on this test.

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    Comment #46140001

    Because the function is not quite correct. It should be return n ? (1u + popcount(n & n - 1u)) : 0u; which both Clang and GCC promptly optimize to a single popcnt.

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    Comment #46011529

    This can be translated to the discrete domain pretty easily, just like the NTT. Pick a sufficiently large prime with order 15k, say, p = 2^61-1. 37 generates the whole multiplicati…

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    Comment #45599873

    No, the generated code seems to be mostly the same as the manual version: https://gcc.godbolt.org/z/aK8orbKE8 The main difference there seems to be that GCC treats the if() as unli…

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    Comment #45481985

    The SIKE comparison is not particularly inconsistent since Bernstein has been banging the drum that structured lattices may not be as secure as thought for years now. Currently the…

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    Comment #45316698

    I thought this was gonna be about the actual Scream stream cipher: https://eprint.iacr.org/2002/019

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    Comment #45111404

    Cimino's Heaven's Gate (1980) is usually pointed as the movie that caused the "no animals were harmed" disclaimer to be added to subsequent movies.

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    Comment #44696747

    Vector ALU instruction latencies are understandably listed as 2 and higher, but this is not strictly the case. From AMD's Zen 5 optimization manual [1], we have The floating point …

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    Comment #44611640

    >Even after the static variable has been initialised, the overhead of accessing it is still considerable: a function call to __cxa_guard_acquire(), plus atomic_load_explicit(&__b_g…

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    Comment #44469816

    The Pentium 4 had branch hints in the form of taken/not taken prefixes. They were not found to be useful and basically ignored in every subsequent Intel microarchitecture, until Re…

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    Comment #44343350

    This circuit [1] puts it at [1] https://nigelsmart.github.io/MPC-Circuits/sha256.txt

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    Comment #44008124

    Karatsuba is definitely faster than schoolbook multiplication at practical sizes. You presumably mean Strassen.

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    Comment #43440767

    In page 10, should the ring R be GF(2)[X]/(X^32-1) and the map p be from {0,1}^{32} to R?

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    Comment #43260150

    Interestingly enough, the Square attack (otherwise more generally known as integral cryptanalysis) is much more powerful than regular linear or differential cryptanalysis when appl…

  19. comment
    Comment #43108600

    Antoine Joux was on the side of classical cryptanalysis on a 2014 bet. This was right after the small-characteristic discrete log advances, so that might no longer be the bet if it…

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    Comment #43082958

    Jasmin is something like this. It is essentially a high-level assembler, will handle register allocation (but not spills) for you, has some basic control flow primitives that map 1…

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    Comment #42857454

    It goes way back; check the work of the likes of Thorsten Holz or Christof Paar. TU Graz is another one.

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    Comment #42638695

    Trying some perf events confirms that there is no extra inserted uop. Going back to the SHLX R[i], R[i], RCX loop, we have: No anomaly: 2,190,954,207 cpu_core/cycles:u/ ( +- 0.14% …

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    Comment #42626996

    Interleaving CQO and SHLX results in ~1.33 throughput with the anomaly, ~2.0 without. This ratio is more or less constant whether it's 1:1 or 2:2 or 4:4 or 8:8 (with 1:1 it's sligh…

  25. comment
    Comment #42610492

    Same framework but instead of, say, SHLX RAX, RAX, RCX I do SHLX R[i], R[i], RCX for 8 consecutive registers. Yes, it still does go to both ports.