IBM debuts sub-1 nanometer chip technology • Hacker News Board

Re: IBM debuts sub-1 nanometer chip technology

#81

Post by dataflow » Thu, Jun 25, 2026, 7:34 PM UTC

vitally3643 wrote: post #55

colechristensen wrote: post #50

Earlier quoted context omitted.

I mean, you can't get smaller than an atom, there is some amount of plausibility of using individual atoms as at least the occasional computing element. Beyond that, engineering a quark-gluon plasma as a processor? I'd watch that Star Trek episode. (we might fantasize about stuff like that but we're roughly monkeys smashing rocks together in a cave vs. building an iPhone sort of gap away from that kind of thing unles…

You could, in principle, use photons and/or electrons. We got pretty damn close in the vacuum tube era, and photonic computing has been a popular research topic for a while. You also have quantum computing, which I think can/does use subatomic particles? Not sure about that one

> You could, in principle, use photons and/or electrons. We got pretty damn close in the vacuum tube era, and photonic computing has been a popular research topic for a while

Wait, what? How does this work in principle for storage? You can store electrons but you're saying you can store photons too?

Re: IBM debuts sub-1 nanometer chip technology

#82

Post by scythe » Thu, Jun 25, 2026, 7:37 PM UTC

adrian_b wrote: post #59

buran77 wrote: post #10

> logic technology can extend for the first time below the 1 nm node, advancing the era of angstrom-level scaling, where dimensions approach the size of individual atoms. While transistor nodes now refer to a generation of manufacturing technology versus an exact physical dimension, IBM’s 0.7 nm technology—also referred to as 7 angstroms—demonstrates how continued scaling remains possible. Continuing the well establi…

As it can be seen from the photos, horizontally the features are much bigger than 5 nm. For silicon, the gate length of a FET has a lower limit somewhere between 10 nm and 15 nm. The current CMOS manufacturing processes have not reached the limit yet. For making smaller transistors, a transition to other semiconductor materials will be necessary. The vertical thicknesses of various layers may be of only a few nanomet…

The scale bar on the far right "photo" (micrograph?) doesn't make sense. It is only slightly less than half the scale bar on the middle photo (10 nm), but the image is clearly scaled up by much more than 2x. Individual silicon atoms are circled in the right photo, but the covalent radius of silicon is about 0.11 nm, so they should be much smaller if the scale bar is accurate.

Re: IBM debuts sub-1 nanometer chip technology

#83

Post by mikko856 » Thu, Jun 25, 2026, 7:39 PM UTC

floxy wrote: post #42

SoftTalker wrote: post #33

Earlier quoted context omitted.

Why above 1mm do we go by tens instead of thousands? We have centimeter (10 mm) then decimeter (100mm) then meter (1000mm). Then we jump to thousand again (kilometer).

>We have centimeter (10 mm) then decimeter (100mm) Does anyone actually use those? I think I would throw up a little in my mouth if I saw either of those on a mechanical drawing.

Centimeter is the commonly used metric for small distances in everyday parlance, just like an inch.

Re: IBM debuts sub-1 nanometer chip technology

#84

Post by xxpor » Thu, Jun 25, 2026, 7:40 PM UTC

victor106 wrote: post #69

Keep hearing that IBM makes these incredible chips but don’t see anyone using IBM chips. What do they do with them?

Approximately everyone (at least in the F500) outside of Big Tech uses them. For example, Costco's entire inventory management system runs on IBM i (so, POWER). You can see the classic terminal look around the store. Banks run a TON of z and i. You'll never see them because they're essentially always in data centers, but I guarantee you interact with them even if it's very non-obvious because there's 50 microservices between the UI and the actual system of record.

Re: IBM debuts sub-1 nanometer chip technology

#85

Post by u1hcw9nx » Thu, Jun 25, 2026, 7:40 PM UTC

buran77 wrote: post #10

> logic technology can extend for the first time below the 1 nm node, advancing the era of angstrom-level scaling, where dimensions approach the size of individual atoms. While transistor nodes now refer to a generation of manufacturing technology versus an exact physical dimension, IBM’s 0.7 nm technology—also referred to as 7 angstroms—demonstrates how continued scaling remains possible. Continuing the well establi…

Unlike marketing terms, "nm density" is actually useful measure.

It describes density measure where you can compare it to planar transistors from the 28-nanometer (28 nm) node around 2010 to 2011 and before. A "0.7 nm" node has equivalent transistor density as if we could have shrunk standard flat transistor node down to 0.7 nanometers.

Re: IBM debuts sub-1 nanometer chip technology

#86

Post by cr3ative » Thu, Jun 25, 2026, 7:42 PM UTC

wmf wrote: post #75

monirmamoun wrote: post #64

Two big problems 1) NOBODY knows what IBM's definition of "sub 1nm" means 2) IBM bullshits so much more than anyone including Intel (remember the "teleportation" ads years ago) that nobody is going to waste time researching what they mean in reality

I know what it means. Something isn't automatically bullshit because it's outside your field of expertise.

“I’m able to parse a marketing term” isn’t a great claim here. Pointing out it’s an unclear term largely abused is valid.

Re: IBM debuts sub-1 nanometer chip technology

#87

Post by xattt » Thu, Jun 25, 2026, 7:42 PM UTC

kailden wrote: post #72

gabrielhidasy wrote: post #67

Earlier quoted context omitted.

Just get better marketers to say your 2nm process has more gates per sqmm than your competition 1nm process.

Exactly. WatsonX AI quantum angstroms for e-business.

Now with Tivoli Monitoring!

Re: IBM debuts sub-1 nanometer chip technology

#88

Post by adrian_b » Thu, Jun 25, 2026, 7:46 PM UTC

wmf wrote: post #49

TallGuyShort wrote: post #35

Earlier quoted context omitted.

I really can't see where the 0.7nm is coming from. The white line looks like it's just an edge of a feature that is "15 rows of silicon atoms", which by some quick arithmetic on Wolfram Alpha has to be AT LEAST ~1.6nm, and the way the rows of atoms appear to be packed in that image and by the provided scale, it seems to be significantly more. Using the white line as a meaningful measurement seems to me to be more mis…

It's the equivalent performance of a 0.7 nm planar transistor. It's not about the feature size.

A 0.7 nm planar transistor made of silicon has no performance, because a device so small cannot function as a transistor.

The intended meaning of "0.7 nm" is that if you compare the transistor density per area of a "0.7 nm" manufacturing process with that of a "350 nm" process (like used for some Pentium II CPUs, at a time when "350 nm" was a real length), the ratio between the transistor densities is (350 nm / 0.7 nm)^2 = 500^2 = 250,000.

Comparing with the number of transistors of a Pentium II, a 0.7 nm CPU should be able to contain about 5000 billion transistors. This is consistent with the fact that the latest 3 nm NVIDIA Rubin GPU has 336 billion transistors and a 0.7 nm circuit must have a density around 16 times greater than a 3 nm circuit.

However, for many of the modern node names used by some companies even this computation is not really true, because marketing may have chosen an arbitrary name that is smaller than for the last process of the main competitor.

For now, IBM has not provided any kind of information that could prove their claim that their new CMOS process has the transistor density corresponding to "0.7 nm" (i.e. 16 times greater than the TSMC "3 nm" CMOS process).

Re: IBM debuts sub-1 nanometer chip technology

#89

Post by measurablefunc » Thu, Jun 25, 2026, 7:47 PM UTC

u1hcw9nx wrote: post #85

buran77 wrote: post #10

> logic technology can extend for the first time below the 1 nm node, advancing the era of angstrom-level scaling, where dimensions approach the size of individual atoms. While transistor nodes now refer to a generation of manufacturing technology versus an exact physical dimension, IBM’s 0.7 nm technology—also referred to as 7 angstroms—demonstrates how continued scaling remains possible. Continuing the well establi…

Unlike marketing terms, "nm density" is actually useful measure. It describes density measure where you can compare it to planar transistors from the 28-nanometer (28 nm) node around 2010 to 2011 and before. A "0.7 nm" node has equivalent transistor density as if we could have shrunk standard flat transistor node down to 0.7 nanometers.

Density is mass per volume so how are you comparing it to a planar transistor? Your units don't even match.

Re: IBM debuts sub-1 nanometer chip technology

#90

Post by bronson » Thu, Jun 25, 2026, 7:50 PM UTC

measurablefunc wrote: post #89

u1hcw9nx wrote: post #85

Earlier quoted context omitted.

Unlike marketing terms, "nm density" is actually useful measure. It describes density measure where you can compare it to planar transistors from the 28-nanometer (28 nm) node around 2010 to 2011 and before. A "0.7 nm" node has equivalent transistor density as if we could have shrunk standard flat transistor node down to 0.7 nanometers.

Density is mass per volume so how are you comparing it to a planar transistor? Your units don't even match.

https://en.wikipedia.org/wiki/Transistor_count#Transistor_de...