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TSMC 2nm Process Disclosure – How Does It Measure Up?

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Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#81

Post by bigtimesink »

wtallis wrote: post #78
ksec wrote: post #59

Earlier quoted context omitted.

N3 is mature and is already in full production for small Mobile SoC only. The Blackwell goes up to ~750mm2 it is a completely different beast. And Nvidia is already having trouble trying to fill up their Blackwell on a higher capacity, relatively mature N4 Node. Imagine doing it on an expensive N3, and then charge $4999 only to get outrage as rip off on HN and reddit. Generally speaking the larger die size, high perf…

Surely you don't believe that large chips like Apple's M3 Max and M4 Max shipped while yields were still immature. So do you think that the wafers per month that TSMC is now cranking out over a year after N3B chips started landing in consumers hands still don't qualify as "full production"? How many fabs need to be fully devoted to 3nm before it is enough volume for you to consider it "full production"?

The number of M3 and M4 SKUs suggests they have yield problems and are disabling bad memory and cores.

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#82

Post by UberFly »

loandbehold wrote: post #72

Why are American fabs built in Arizona? What's so special about AZ?

Main reasons are a stable geology and climate, access to reliable water via the salt river project that was designated for industrial use, and the historical semiconductor presence that is already in the area. The local universities also have a strong focus on tech.

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#83

Post by wuschel »

fngjdflmdflg wrote: post #42
wuschel wrote: post #32

Earlier quoted context omitted.

What do you tbink is holding RiscV core design back? Is it the IP situation?

Not a hardware person but I read in an interview with Jim Keller that ISA itself doesn't matter that much for performance. >[Arguing about instruction sets] is a very sad story. It's not even a couple of dozen [op-codes] - 80% of core execution is only six instructions - you know, load, store, add, subtract, compare and branch. With those you have pretty much covered it. If you're writing in Perl or something, maybe…

Thanks for the answer and reference!

> Not sure if that is what you meant by IP here.

By IP I meant intellectual property. I was wondering how much designs or specific hardware developments that were essential for the performance boost (or: energy efficiency of chips, compute/W) as observed with the Apple M family of designs are locked down by patents.

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#84

Post by wtallis »

bigtimesink wrote: post #81
wtallis wrote: post #78

Earlier quoted context omitted.

Surely you don't believe that large chips like Apple's M3 Max and M4 Max shipped while yields were still immature. So do you think that the wafers per month that TSMC is now cranking out over a year after N3B chips started landing in consumers hands still don't qualify as "full production"? How many fabs need to be fully devoted to 3nm before it is enough volume for you to consider it "full production"?

The number of M3 and M4 SKUs suggests they have yield problems and are disabling bad memory and cores.

"Disabling bad memory" as in DRAM isn't a thing that happens, to anybody. DRAM is made in its own fabs and goes through QA before being packaged. So whether it lands onto DIMMs or in a SoC package, it's known-good dies that are being used.

And you cannot look at the number of SKUs without also taking into account how many different die designs are being manufactured and binned to produce that product line. Intel and AMD CPUs have far more bins per die, and usually fewer different die sizes as a starting point. Apple isn't manufacturing a M3 Max and sometimes binning that down to a M3 Pro, or a M3 Pro down to a M3. You're really just seeing about two choices for enabled core count from each die, which is not any kind of red flag.

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#85

Post by magicalhippo »

hcfman wrote: post #37
magicalhippo wrote: post #13

Earlier quoted context omitted.

The current Pi 5 is on a 16nm node[1], down from 28nm for the Pi 4. So, far off needing a bleeding edge node[2] to see further improvements. [1]: https://chipwise.tech/our-portfolio/raspberry-pi-5/ [2]: https://www.tsmc.com/english/dedicatedFoundry/technology/log...

The Pi is great! Just saying, running a Pi with an object detector on batteries draws around 9W. That's big batteries and solar or wildlife use cases. But think how cool it would be if it could run on 2W. Having said that. The Jetson runs at around 7W doing that and a lot faster inference. Just a lot more expense. Likely the Jetson will eventually be something like 2nm. So maybe we see around 4W at that time running…

Jetson Nano was manufactured using the 20nm node as far as I can see[1].

Just goes to show manufacturing node isn't everything. There's a lot of various optimizations one can do depending on targets.

Guess we'll just have to see what the future brings.

[1]: https://en.wikipedia.org/wiki/Tegra#Tegra_X1

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#86

Post by bigtimesink »

josaka wrote: post #73
loandbehold wrote: post #72

Why are American fabs built in Arizona? What's so special about AZ?

I suspect it's, in part, because humidity is low. The fab needs to tightly control humidity and temperature. Pulling water from air is energy intensive. Facilities team in the fab I used to work in said their most energy intensive days where the most humid days.

Humidity in Taiwan can be very high.

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#87

Post by caycep »

adrian_b wrote: post #51
sylware wrote: post #2

So, Intel has its better "18A" process and we have no idea when they will start production at scale and where? Weird.

The first Intel product on 18A is the "Panther Lake" CPU for laptops. According to what Intel claims, it will be launched in H2 2025, i.e. with commercial availability either in October or in December, depending on how quickly Intel will succeed to improve the yields of the 18A process.

Who's running the show now that Gelsinger is out?

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#88

Post by adgjlsfhk1 »

wuschel wrote: post #32
adgjlsfhk1 wrote: post #22

Earlier quoted context omitted.

Riscv doesn't need smaller nm. It just needs someone to actually design and release a good core design. 14nm (or 4 or anything in between) is perfectly suffient to make a Riscv chip 10x faster than any Riscv that currently exist.

What do you tbink is holding RiscV core design back? Is it the IP situation?

Building a chip is really hard, and the companies that have experience all have their own architecture that they like and no reason to make a high performance design that competes with their regular chips.

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#89

Post by phonon »

wtallis wrote: post #84
bigtimesink wrote: post #81

Earlier quoted context omitted.

The number of M3 and M4 SKUs suggests they have yield problems and are disabling bad memory and cores.

"Disabling bad memory" as in DRAM isn't a thing that happens, to anybody. DRAM is made in its own fabs and goes through QA before being packaged. So whether it lands onto DIMMs or in a SoC package, it's known-good dies that are being used. And you cannot look at the number of SKUs without also taking into account how many different die designs are being manufactured and binned to produce that product line. Intel and…

Memory = on chip cache. M4Max has loads of it....

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#90

Post by wtallis »

phonon wrote: post #89
wtallis wrote: post #84

Earlier quoted context omitted.

"Disabling bad memory" as in DRAM isn't a thing that happens, to anybody. DRAM is made in its own fabs and goes through QA before being packaged. So whether it lands onto DIMMs or in a SoC package, it's known-good dies that are being used. And you cannot look at the number of SKUs without also taking into account how many different die designs are being manufactured and binned to produce that product line. Intel and…

Memory = on chip cache. M4Max has loads of it....

Disabling cache as a binning strategy isn't too common these days, unless it's a cache slice associated with a CPU or GPU core that's being disabled. Large SRAMs are manufactured usually with some spare cache lines so that they can tolerate a few defects while still operating with the nominal capacity. SRAM defects are usually not the driving force behind a binning decision.

Back when Intel was stagnant at 4 cores for the bulk of their consumer CPU product line, they did stuff like sell i7 parts with 8MB L3 cache and i5 parts with 6MB cache, more as a product segmentation strategy than to improve yields (they once infamously sold a CPU with 3MB last level cache and later offered a software update to increase it to 4MB, meaning all chips of that model had passed binning for 4MB). Nowadays Intel's cache capacities are pretty well correlated with the number of enabled cores. AMD usually doesn't vary L3 cache sizes even between parts with a different number of enabled cores: you get 32MB per 8-core chiplet, whether you have 8 cores or 6 cores enabled.

I don't know to what extent the cache sizes on Apple's chips vary between bins, but it probably follows the pattern of losing only cache that's tied to some other structure that gets disabled.

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