71–79 of 79 posts
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Monitors and TVs absolutely do. And it's not unheard of for them to have FPGAs for that reason.
I guess one could consider the video hardware decoder a FPGA, although I would bet that the smart models just use a GPU in some SOC model instead.
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I thought FPGAs were more power efficient than GPUs for many ML applications for example (CNNs aside)?
For unusual ML architectures, like 1 bit precision, that might be true. For anything using floating point maths, it isn't true.
Substantial gains in terms of performance per watt for FPGAs?
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This is somewhat orthogonal to what you are saying, but I’ve wondered for a while if it’s possible to achieve vertical and horizontal abstraction at the same time. When you are working on the actual implementations, horizontal style is clearly preferable, but if you want to change the abstraction, the vertical style is much easier. The limitation of just one being accessible at a time seems to purely be a consequence…
In a way, the VexRiscv is already implemented in both directions: While stages are specified individually, you can declare those stages to collapse together. The VexRiscv can be specified to be between 2 and 5 stages. In terms of readability, you still have the 5 stages separated out within the same file.
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Intel has the Cyclone V range. Also, I've never done it myself but I've read that digikey prices are almost never the actual price for FPGAs even in relatively small quantities (haggling with avnet).
Well, that is true for all components at digikey. You don't mass-produce stuff with components bought from DK (or avnet either, for that matter, depending on where you do your production)
I looked up a random i.MX6 processor from NXP. It’s $32.08 for one of them, and $20.95 per part when you get a reel of 500. If you need a few thousand units made, it’s perfectly reasonable to order parts from Digi-Key. You might be overpaying compared to what a good purchasing person can get you, but it’s fine for a few thousand parts, and quick and easy.
Look up any Xilinx part on Digi-Key, and there’s just a single price break at 1 unit. Even Lattice parts only go up to price breaks of 100.
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Well Xilinx has the Zynq-7000 SoC[1], featuring an ARM Cortex-A9 CPU along with a potentially quite large FPGA. Not exactly cheap though, at least in small quantities[2] [1]: https://www.xilinx.com/products/silicon-devices/soc/zynq-700... [2]: https://www.digikey.com/products/en/integrated-circuits-ics/...
Intel has the Cyclone V range. Also, I've never done it myself but I've read that digikey prices are almost never the actual price for FPGAs even in relatively small quantities (haggling with avnet).
While i don't care so much about the systems they emulate, and the cores they offer, this seems like a nice place to get started because of the many examples one can learn from.
Also Intel themselves offer many tutorials for it, on github and elsewhere.
And it creates an 'ecosystem' of reasonably available hardware expansions, without the usual markup for that stuff, should one need, or want them.
Would i start today, i'd use this. As it is, i've spent much more for similar stuff in the past.
I approve!
I'm disappointed today's general purpose CPU's and microcontrollers don't come with some integrated FPGA space, similar to how you have SRAM and other peripherals. Intel talked about it a few years back [1] but I'm not sure anything materialized. The closest I've seen in popular chips is a few gates worth of programmable logic. Are there any hidden gems I've missed out on? [1] https://www.nextplatform.com/2018/05/24/…
There was a company that had an FPGA implementation of HyperTransport so that you could link the FPGA to a network of AMD Opteron CPUs.
FPGA Noob here. I have 2 questions about FPGA's that I'm hoping someone here can help me out with: 1. For the FPGAs i've looked at, you seem to have to initially configure them before being able to run your programs on them, kind of like EEPROM. I feel it would be much more interesting from a reconfigurable computing perspective if the devices were able to programatically re-configure on the fly as easily as it is to…
I didn't find what clock rate it runs at. It mentions booting linux in 4 seconds, but that is hard to extrapolate into a core clock frequency. 100 MHz? 200 MHz? higher?
Doesn't that depend on the FPGA you use?
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Doesn't that depend on the FPGA you use?
Of course, but he article author did build it on a specific system and said the boot speed, so saying that clock rate would have also been a useful data point if the platform is known. Someone using a different FPGA could use rough scaling factor to guesstimate what they might achieve for the platform they have on hand.
We've yet to make detailed analyses on the multicore version, but in general I'd say it's pretty decent.