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SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3

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Re: SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3

#61
post #20

HBM2 is like 2Tb/s, how is HBM3 7GB/s ?

HBM3 was expected to be like 4GB/s per pin which was seen as double HBM2 per pin, so this is therefore almost even double that, which is good news

The HBM2 total memory bandwidth is like 2TB/s, just different scale

Anyway I could totally be using wrong nomenclature and terminology, feel free to discuss, these aren't assertions or aren’t strongly held assertions

Re: SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3

#62
post #55
post #41

Earlier quoted context omitted.

You would love to see computers become harder to program?

It canbe nice to have the opportunity to program something harder but faster. Counter example: Itanium, which was too hard to program (compilers) for.

It is kind of ironic that compiler theory has advanced and now we can target Itanium no problem. It was a bit (well, a lot) ahead of its time.

Re: SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3

#63
post #41

HBM might be an interesting idea. I would love to see multiple bandwidth levels of memory becoming a norm, with computers a very fast small amount of memory, and a larger set of DRR4 or DRR5. We already have multiple levels of cache, why not having multiple levels of RAM? Operating systems and software would need to accommodate a new reality where NUMA is the norm though. But it’s good that we even have the concept o…

You would love to see computers become harder to program?

I would try to build a new compiler (or a LLVM intermediary processing layer) that does NUMA optimizations.

Re: SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3

#64
post #3

I know they're separate lines and capacity is sold well in advance and all that, but this chip shortage still baffles me. A startup can tape out a 5 nm chip, but STMicroelectronics can't make any of their 40-130 nm microcontrollers for the next year? Also car companies are supposedly the culprit, even though their volume is only in the low tens of millions per year, and the dustup is apparently over only six months o…

ST fabs their own chips. If their fabs don't have the capacity, it's a huge slog to tape them out to a radically different process at another company.

Re: SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3

#65
post #2

How did SiFive get anywhere near 5nm TSMC?

They pay money just like any other customer of TSMC. SiFive has a lot of buzz in the industry. I wouldn't be surprised that TSMC wanted to work with them. But there are other intermediary companies that help startups group multiple chips from multiple companies together into a single mask. This is called a "shuttle" and allows the companies to split the costs of the masks (I've heard up to $30 million for 5nm) SiFive…

Adding to this, it's in TSMC's interest to have cheaper licenses for high quality processor cores for it's customers, and therefore have strategic reasons to prioritize small runs of RISC-V chips right now.

Pretty classic "commoditize your complement".

Re: SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3

#66

Earlier quoted context omitted.

Thousands to tens of thousands per car? I think you're off by an order of magnitude.

I know a typical Mercedes has roughly a hundred individual computers, not too far reached to think the average chip count could be 10 or higher per device on the can bus.

Most of those chips would be standard commodity silicon components (think op-amps and such) as opposed to purpose-built automotive micro controllers.

Re: SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3

#67

Earlier quoted context omitted.

Indeed yes I meant cells, I'm not a native English speaker. > At electric-car scales, you have thousands-and-thousands of cells. You can't just manage all of them with one IC, so you build an IC per bundle. Maybe 48 cells or 100-cells per IC or so. Ah okay, I had more expected something on the order of 1 IC per 4 cells to allow individual cell health monitoring.

> Indeed yes I meant cells, I'm not a native English speaker. You're doing fine. Native English speakers don't know the difference between cell or battery either. This is more of a precise / technical engineering distinction. * 9V Battery ( https://imgur.com/FHJdhIK ), a collection of 6x cells. * AAAA Cell (one singular chemical reaction of 1.5V) Notice that the imgur is wrong: they call it a AAAA battery (when the p…

In Russian the word "battery" is most commonly used to mean a hot water radiator in an apartment.

Which is a collection of fins.

An electrical battery is called akkumulator.

Re: SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3

#68
post #45

Earlier quoted context omitted.

High voltage MOSFETs and IGBTs are built on a completely different process. Size is definitely not an issue with them. It is about exotic doping to create the desired characteristics. They're built using much larger feature sizes but on completely separate lines.

I'm not really in the industry. But I know that high-voltage MOSFETs / IGBTs need substantial amounts of current to turn on / off adequately. Under typical use, there's a dedicated chip called a "Gate Driver" that provides that current, between a microcontroller and the IGBT. Its not that the IGBT / MOSFETs are built on these microcontrollers. Its that the Gate-Driver can be integrated into a microcontroller (simplif…

Gate drivers are discrete parts and aren't integrated into microcontorllers because they require high voltages (12/24V vs 3.3V) amongst many other reasons.

They also have to be located close to the IGBT and the designers would want it as a separate part because it gives them enormous flexibility. You aren't saving much by adding a gate driver to a micro and I can't think of any micro that has it integrated. There are simple things like motor drivers, etc. that may have a gate driver integrated but that's not a micro and those are also built on large nodes -- much larger than nodes used for microcontrollers.

FWIW: I design advanced node (20-5nm) ASICs for a living, and have designed on older nodes before. I've also worked in power electronics.

Re: SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3

#69

Earlier quoted context omitted.

Almost everything in a car has a number of chips. Power regulations, communication buses... and in electric cars with thousands of batteries, at least one chip per battery for protection.

Electric cars have ONE battery with thousands of *cells*. I do realize that the colloquial term for "cell" is "battery" (ex: an AA cell is called a battery), but it becomes important to be precise with our words when talking about manufacturing. Small scale Li-ion does a protection-IC per cell (ex: cell phones), mostly because cell phones are so small they only use one cell. Larger scale Li-ion, such as Laptop batter…

I always thought the "cell" in "cellular phone" came from the network topology, not the battery format.

Re: SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3

#70
post #2

How did SiFive get anywhere near 5nm TSMC?

They pay money just like any other customer of TSMC. SiFive has a lot of buzz in the industry. I wouldn't be surprised that TSMC wanted to work with them. But there are other intermediary companies that help startups group multiple chips from multiple companies together into a single mask. This is called a "shuttle" and allows the companies to split the costs of the masks (I've heard up to $30 million for 5nm) SiFive…

Can you list some of these shuttle companies? What are the most popular/reputable ones?
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