HBM2 is like 2Tb/s, how is HBM3 7GB/s ?
I think that’s per-Pin bandwidth?
SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3
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Re: SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3
#22IIRC, 32-bit RISC-V is only intended for deep embedded workloads, with 64-bit for general purpose compute. So a SoC w/ a single 32-bit core would seem to be a less-than-ideal fit for the cutting-edge 5nm process.
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Re: SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3
#23I know they're separate lines and capacity is sold well in advance and all that, but this chip shortage still baffles me. A startup can tape out a 5 nm chip, but STMicroelectronics can't make any of their 40-130 nm microcontrollers for the next year? Also car companies are supposedly the culprit, even though their volume is only in the low tens of millions per year, and the dustup is apparently over only six months o…
This is an extremely low volume prototype run. You can get those scheduled on short notice. Fabs love them because they can do process optimization using them, without impacting production customers. They're ridiculously expensive per-die and you commit to accept a much higher failure rate than normal. ST can and is making microcontrollers. It's just that they've sold their production for a year ahead, before it's ev…
Thousands to tens of thousands per car? I think you're off by an order of magnitude.
Re: SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3
#24Earlier quoted context omitted.
This is an extremely low volume prototype run. You can get those scheduled on short notice. Fabs love them because they can do process optimization using them, without impacting production customers. They're ridiculously expensive per-die and you commit to accept a much higher failure rate than normal. ST can and is making microcontrollers. It's just that they've sold their production for a year ahead, before it's ev…
Thousands to tens of thousands per car? I think you're off by an order of magnitude.
Almost everything in a car has a number of chips. Power regulations, communication buses... and in electric cars with thousands of batteries, at least one chip per battery for protection.
Re: SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3
#25Earlier quoted context omitted.
This is an extremely low volume prototype run. You can get those scheduled on short notice. Fabs love them because they can do process optimization using them, without impacting production customers. They're ridiculously expensive per-die and you commit to accept a much higher failure rate than normal. ST can and is making microcontrollers. It's just that they've sold their production for a year ahead, before it's ev…
Thousands to tens of thousands per car? I think you're off by an order of magnitude.
I know a typical Mercedes has roughly a hundred individual computers, not too far reached to think the average chip count could be 10 or higher per device on the can bus.
Re: SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3
#26Earlier quoted context omitted.
Thousands to tens of thousands per car? I think you're off by an order of magnitude.
Almost everything in a car has a number of chips. Power regulations, communication buses... and in electric cars with thousands of batteries, at least one chip per battery for protection.
This is blatantly false, unless you are confusing battery for an assembled battery pack. In EVs each battery management IC can run somewhere in the range of 4-14 cells in series per chip, and they almost universally run banks of up to 100 cells in parallel. For example, in the tesla model s the pack is comprised into submodules of 76 cells in parallel and 6 of those groups in series per management chip--so only one management chip per 456 cells.
Re: SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3
#27Earlier quoted context omitted.
Thousands to tens of thousands per car? I think you're off by an order of magnitude.
Almost everything in a car has a number of chips. Power regulations, communication buses... and in electric cars with thousands of batteries, at least one chip per battery for protection.
Electric cars have ONE battery with thousands of *cells*. I do realize that the colloquial term for "cell" is "battery" (ex: an AA cell is called a battery), but it becomes important to be precise with our words when talking about manufacturing.
Small scale Li-ion does a protection-IC per cell (ex: cell phones), mostly because cell phones are so small they only use one cell.
Larger scale Li-ion, such as Laptop batteries, may use one-IC per cell, OR one-protection IC for all 3x or 4x cells combined. As long as all the cells are soldered together, one protection IC is cheaper and still usable.
At electric-car scales, you have thousands-and-thousands of cells. You can't just manage all of them with one IC, so you build an IC per bundle. Maybe 48 cells or 100-cells per IC or so.
Re: SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3
#28I know they're separate lines and capacity is sold well in advance and all that, but this chip shortage still baffles me. A startup can tape out a 5 nm chip, but STMicroelectronics can't make any of their 40-130 nm microcontrollers for the next year? Also car companies are supposedly the culprit, even though their volume is only in the low tens of millions per year, and the dustup is apparently over only six months o…
A lot of chips are made on mature fab lines because they don't need the performance of 5nm lines or can't justify the mask costs. No one is investing in mature fab lines because they're not leading edge and they're being run to amortize the initial investmnet made into them years ago. Therefore not much additional capacity for mature lines. So yes you can see 5nm chips being taped out but the 40-130nm chips are squee…
> A lot of chips are made on mature fab lines because they don't need the performance of 5nm lines or can't justify the mask costs.
Alternatively: they're car-scale products dealing primarily with high electric currents (10s or 100s of milliamps) and/or higher voltages (5V instead of 1.3V).
Smaller chips use (and therefore output) less current than larger scale chips. But if your goal is to output 10mA to better drive an IGBT or other transistor anyway, then you really prefer 40nm to 130nm ANYWAY, because those larger sizes are just a lot better at moving those large currents around.
Bigger wires mean bigger currents.
Re: SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3
#29HBM2 is like 2Tb/s, how is HBM3 7GB/s ?
HBM3 wasn't just supposed to be about speed. It also offers a 512-bit option that doesn't require a silicon interposer. I'd guess this was added to make cheaper consumer GPU designs possible.
I suspect they're using the HBM2 spec for the narrow bus and cheaper interposer while keeping speeds lower and only using a couple stacks instead of the 16 or so HBM2 stacks required for those 2Tb/s speeds you mention. It makes sense given that their chip likely couldn't use a huge amount of bandwidth anyway.
Re: SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3
#30IIRC, 32-bit RISC-V is only intended for deep embedded workloads, with 64-bit for general purpose compute. So a SoC w/ a single 32-bit core would seem to be a less-than-ideal fit for the cutting-edge 5nm process.
The core is supposed to compete with the Cortex M7. The smallest process M7 I can find is the STM32H7, which is 40nm.