MIPS Becomes RISC-V • Hacker News Board

Re: MIPS Becomes RISC-V

#61

Post by bitwize » Mon, Mar 08, 2021, 8:13 PM UTC

Fordec wrote: post #59

MaxBarraclough wrote: post #36

Everyone's right to celebrate the success of RISC-V, but part of me thinks it's a shame that there's relatively little architectural diversity ( edit I should have said ISA diversity ) in modern CPUs. MIPS, Alpha, and Super-H, have all but faded away. Power/PowerPC is still out there somewhere though. Apparently they're still working on SPARC, too. [0] At least we'll always have the PS2. ...until the last one breaks,…

We need diversity for solving different problems, not for diversity sake. What problem did MIPS solve in a unique way that others didn't? Because it wasn't desktop, mobile, embedded, graphics or AI.

MIPS was a nice simple ISA for CE students to learn and implement. Both ARM and RISC-V have gotchas that make them more complicated.

I suppose it will live on in that form, especially if the IP is opened up.

Re: MIPS Becomes RISC-V

#62

Post by yjftsjthsd-h » Mon, Mar 08, 2021, 8:17 PM UTC

Fordec wrote: post #59

MaxBarraclough wrote: post #36

Everyone's right to celebrate the success of RISC-V, but part of me thinks it's a shame that there's relatively little architectural diversity ( edit I should have said ISA diversity ) in modern CPUs. MIPS, Alpha, and Super-H, have all but faded away. Power/PowerPC is still out there somewhere though. Apparently they're still working on SPARC, too. [0] At least we'll always have the PS2. ...until the last one breaks,…

We need diversity for solving different problems, not for diversity sake. What problem did MIPS solve in a unique way that others didn't? Because it wasn't desktop, mobile, embedded, graphics or AI.

Throwing out diversity because you don't see any immediate benefit is a great way to not have it when a different problem does show up.

I don't know about unique way, but MIPS certainly was good at embedded; there's plenty of networking gear using it.

Re: MIPS Becomes RISC-V

#63

Post by dang » Mon, Mar 08, 2021, 8:18 PM UTC

throwaway81523 wrote: post #54

Actual source: https://www.eejournal.com/article/wait-what-mips-becomes-ris...

Right. We changed the URL from https://tuxphones.com/mips-joins-risc-v-open-hardware-standa..., which points to that. Thanks!

Re: MIPS Becomes RISC-V

#64

Post by nickysielicki » Mon, Mar 08, 2021, 8:21 PM UTC

This article from 2015 ("The Death of Moore’s Law Will Spur Innovation: As transistors stop shrinking, open-source hardware will have its day") is getting better and better with age.

https://spectrum.ieee.org/semiconductors/design/the-death-of...

Re: MIPS Becomes RISC-V

#65

Post by einpoklum » Mon, Mar 08, 2021, 8:22 PM UTC

Does this mean that design features from MIPS can now be adopted / adapted in RISC-V? Or is it just a no-longer-used ISA and chip designs that become freely usable?

Re: MIPS Becomes RISC-V

#66

Post by schoen » Mon, Mar 08, 2021, 8:22 PM UTC

bitwize wrote: post #61

Fordec wrote: post #59

Earlier quoted context omitted.

We need diversity for solving different problems, not for diversity sake. What problem did MIPS solve in a unique way that others didn't? Because it wasn't desktop, mobile, embedded, graphics or AI.

MIPS was a nice simple ISA for CE students to learn and implement. Both ARM and RISC-V have gotchas that make them more complicated. I suppose it will live on in that form, especially if the IP is opened up.

I remember CS 61C at Berkeley used to use MIPS to teach assembly language programming and a bit about computer architecture, using the original MIPS version of Patterson and Hennessy's Computer Organization and Design. Now that book is available in both MIPS and RISC-V versions, with, I've assumed, much more effort going into the RISC-V version...

I do think the simplicity of MIPS was a big plus there, including simplicity of simulating it (http://spimsimulator.sourceforge.net/). I suppose a lot of students may appreciate being taught on something that is or is about to be very widely used, even if it's more complicated in various ways -- and the fact that one of the textbook authors was a main RISC-V designer makes me assume that educational aspects are not at all neglected in the RISC-V world.

Re: MIPS Becomes RISC-V

#67

Post by Gracana » Mon, Mar 08, 2021, 8:27 PM UTC

zokier wrote: post #24

tyingq wrote: post #17

Earlier quoted context omitted.

Fujitsu for general purpose servers, and Atmel (maybe others too?) for rad-hardened Sparc.

> Atmel Microchip these days, Atmel got acquired few years back.. The packaging looks cool of those https://www.microchip.com/wwwproducts/en/AT697F

That's how it's packaged prior to trimming and lead forming, which looks like this:

https://www.youtube.com/watch?v=4CfEN5R13w4

Re: MIPS Becomes RISC-V

#68

Post by capableweb » Mon, Mar 08, 2021, 8:28 PM UTC

yjftsjthsd-h wrote: post #62

Fordec wrote: post #59

Earlier quoted context omitted.

We need diversity for solving different problems, not for diversity sake. What problem did MIPS solve in a unique way that others didn't? Because it wasn't desktop, mobile, embedded, graphics or AI.

Throwing out diversity because you don't see any immediate benefit is a great way to not have it when a different problem does show up. I don't know about unique way, but MIPS certainly was good at embedded; there's plenty of networking gear using it.

> MIPS certainly was good at embedded

As far as I understand, it's not that MIPS is the best at embedded, it's just that it's cheaper to sell as the license cost is non-existing and good support already exists in kernels and so on.

Re: MIPS Becomes RISC-V

#69

Post by throwaway_6142 » Mon, Mar 08, 2021, 8:29 PM UTC

Narishma wrote: post #42

moistbar wrote: post #31

Earlier quoted context omitted.

That's what I got from it, but I have to say I don't understand the decision to throw away such a storied architecture as MIPS. I mean come on, the N64 runs on it!

PS1, PS2 and PSP also used MIPS processors and were each much more successful than the N64.

Atmel

Re: MIPS Becomes RISC-V

#70

Post by tyingq » Mon, Mar 08, 2021, 8:37 PM UTC

The MIPS name was originally was an acronym for "Microprocessor without Interlocked Pipeline Stages". The RISC-V docs that I've skimmed seem to show quite a lot more hardware pipeline interlocking than the last gen MIPS processors. So the name is a bit funny now.