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SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3

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Re: SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3

#51

Post by rowanG077 »

jankeymeulen wrote: post #23
Kliment wrote: post #9

Earlier quoted context omitted.

This is an extremely low volume prototype run. You can get those scheduled on short notice. Fabs love them because they can do process optimization using them, without impacting production customers. They're ridiculously expensive per-die and you commit to accept a much higher failure rate than normal. ST can and is making microcontrollers. It's just that they've sold their production for a year ahead, before it's ev…

Thousands to tens of thousands per car? I think you're off by an order of magnitude.

What? You think it's ten thousands to hundred thousand. Hundred thousand seems excessive to me.

Re: SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3

#52

Post by bogomipz »

lizknope wrote: post #10
ohazi wrote: post #3

I know they're separate lines and capacity is sold well in advance and all that, but this chip shortage still baffles me. A startup can tape out a 5 nm chip, but STMicroelectronics can't make any of their 40-130 nm microcontrollers for the next year? Also car companies are supposedly the culprit, even though their volume is only in the low tens of millions per year, and the dustup is apparently over only six months o…

I'm in the semiconductor company. I don't really understand your question. Anyone can start a company and tape out a chip even in 5nm. My previous startup did something similar. We used an intermediate company between us and TSMC that specifically works with smaller companies. They (or TSMC) will bundle together 4 to 20 chips into a common mask as a "shuttle" run. Shuttle runs are really only used to get samples for…

>" Shuttle runs are really only used to get samples for the first version of your chip."

Is a "tape out" the same thing as a shuttle run/sample chip run?

Re: SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3

#53

Post by makapuf »

tyingq wrote: post #30
zozbot234 wrote: post #13

IIRC, 32-bit RISC-V is only intended for deep embedded workloads, with 64-bit for general purpose compute. So a SoC w/ a single 32-bit core would seem to be a less-than-ideal fit for the cutting-edge 5nm process.

The core is supposed to compete with the Cortex M7. The smallest process M7 I can find is the STM32H7, which is 40nm.

I rave for stm32 with high end processes (10nm or less), whether that makes sense or not. I just love stm32..

Re: SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3

#54

Post by justincormack »

zozbot234 wrote: post #13

IIRC, 32-bit RISC-V is only intended for deep embedded workloads, with 64-bit for general purpose compute. So a SoC w/ a single 32-bit core would seem to be a less-than-ideal fit for the cutting-edge 5nm process.

I think it means 32 bit floating point, not 32 bit CPU, as it mentions "other relatively simplistic applications that do not require full precision" but its a bit unclear.

Re: SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3

#55

Post by makapuf »

wmf wrote: post #41
winter_blue wrote: post #35

HBM might be an interesting idea. I would love to see multiple bandwidth levels of memory becoming a norm, with computers a very fast small amount of memory, and a larger set of DRR4 or DRR5. We already have multiple levels of cache, why not having multiple levels of RAM? Operating systems and software would need to accommodate a new reality where NUMA is the norm though. But it’s good that we even have the concept o…

You would love to see computers become harder to program?

It canbe nice to have the opportunity to program something harder but faster. Counter example: Itanium, which was too hard to program (compilers) for.

Re: SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3

#56

Post by throwaway4good »

01100011 wrote: post #50
throwaway4good wrote: post #49

What is the use case of this chip? I have the feeling it is some way away from a general purpose CPU / SOC like the Apple M1?

RTFA? > The SoC can be used for AI and HPC applications and can be further customized by SiFive customers to meet their needs. Meanwhile, elements from this SoC can be licensed and used for other N5 designs without any significant effort. > The SoC contains the SiFive E76 32-bit CPU core(s) for AI, microcontrollers, edge-computing, and other relatively simplistic applications that do not require full precision.

So it is a proof of concept / demo of subcomponents someone else may license? Is that a correct interpretation?

Re: SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3

#57

Post by Kliment »

bogomipz wrote: post #52
lizknope wrote: post #10

Earlier quoted context omitted.

I'm in the semiconductor company. I don't really understand your question. Anyone can start a company and tape out a chip even in 5nm. My previous startup did something similar. We used an intermediate company between us and TSMC that specifically works with smaller companies. They (or TSMC) will bundle together 4 to 20 chips into a common mask as a "shuttle" run. Shuttle runs are really only used to get samples for…

>" Shuttle runs are really only used to get samples for the first version of your chip." Is a "tape out" the same thing as a shuttle run/sample chip run?

a "tape out" is the process of transforming a design into a physical die - i.e. a manufacturing run. It's when you hand over a design to a foundry to do their thing with it.

Re: SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3

#58

Post by phendrenad2 »

justincormack wrote: post #54
zozbot234 wrote: post #13

IIRC, 32-bit RISC-V is only intended for deep embedded workloads, with 64-bit for general purpose compute. So a SoC w/ a single 32-bit core would seem to be a less-than-ideal fit for the cutting-edge 5nm process.

I think it means 32 bit floating point, not 32 bit CPU, as it mentions "other relatively simplistic applications that do not require full precision" but its a bit unclear.

The quote that stands out to me is that the core is "ideal for applications which require high performance -- but have power constraints (e.g., Augmented Reality and Virtual Reality , IoT Edge Compute, Biometric Signal Processing, and Industrial Automation)."

Re: SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3

#59

Post by jandrese »

dragontamer wrote: post #32
zozbot234 wrote: post #13

IIRC, 32-bit RISC-V is only intended for deep embedded workloads, with 64-bit for general purpose compute. So a SoC w/ a single 32-bit core would seem to be a less-than-ideal fit for the cutting-edge 5nm process.

Routers / Switches have extremely weird performance characteristics, and I think that's what SiFive is targeting with this chip. * HBM3 for the highest memory bandwidth (10Gbps switches need tons and tons of bandwidth. That's 10Gbps per direction per connection, 8x ports is 160Gbps, and then that's multiplied multiple times over by every memcpy / operation your chip actually does. You need to DELIVER 160Gbps, which m…

IPv6 address comparison on a 32 bit design is fairly awkward. Switches won't care, but routers need to make routing decisions.

Re: SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3

#60

Post by sanxiyn »

throwaway4good wrote: post #56
01100011 wrote: post #50

Earlier quoted context omitted.

RTFA? > The SoC can be used for AI and HPC applications and can be further customized by SiFive customers to meet their needs. Meanwhile, elements from this SoC can be licensed and used for other N5 designs without any significant effort. > The SoC contains the SiFive E76 32-bit CPU core(s) for AI, microcontrollers, edge-computing, and other relatively simplistic applications that do not require full precision.

So it is a proof of concept / demo of subcomponents someone else may license? Is that a correct interpretation?

Yes.
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