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AMD Tackles Coming “Chiplet” Revolution With New Chip Network Scheme

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Re: AMD Tackles Coming “Chiplet” Revolution With New Chip Network Scheme

#51

Post by daveguy »

greglindahl wrote: post #32
sixdimensional wrote: post #30

I wonder if FPGAs could be a node too. That would allow us to mix programmable, highly parallel analog modeled acceleration onto the same high speed / direct connect bus as all the other fixed, traditional computing components. I really like the approach AMD is suggesting here, treating it like nodes on a network.

You've been able to buy FPGAs tightly coupled with AMD CPUs since 2006 or so. The tech back then was to either plug them into an HTX Hypertransport slot, or in a cpu socket. Very few customers actually wanted to buy these things and I think all of the makers lost money.

They definitely are missing an application that probably won't be coming until specialized chip designs are a commodity (eg agi+). Right now you can get specialized chips for much less than the cost of the programmable chip + custom design. Once a company identifies a kick-ass fpga design (and it has any decent market) they move to asic to drive down costs. I guess if fpga costs were as low as an asic it would be viable as you could change the application depending on current needs. But currently fpga chips are 10-100x the cost of asics.

Re: AMD Tackles Coming “Chiplet” Revolution With New Chip Network Scheme

#53

Post by st26 »

paulmd wrote: post #48
dragontamer wrote: post #21

The main issue AMD seems to be solving here is the yields at 7nm and lower processes. Smaller chips means that you get more yield in the presence of errors. Intel builds relatively large 600mm^2 chips (like the XCC aka the 28-core Xeon), but AMD thinks the future is to build networks of ~200mm^2 chips, like what they've done with Zen / Threadripper / EPYC. The advantage for AMD is that they've built a single design:…

> The advantage for AMD is that they've built a single design: the Zeppelin die. RyZen is simply one Zeppelin. Threadripper is two Zeppelins. And EPYC is four Zeppelins. While a popular meme, this is not actually true. Epyc is actually a totally different die, stepping B2 vs the B1 die used in Ryzen+TR. https://en.wikichip.org/wiki/amd/ryzen_7/1800x https://en.wikichip.org/wiki/amd/epyc/7601 The 2700X is actually on…

Steppings are minor revisions, perhaps analogous to a kernel patch revision. So they do have to manufacture B2 die and B1 die and they are not interchangeable- but they are 99.999% identical.

Re: AMD Tackles Coming “Chiplet” Revolution With New Chip Network Scheme

#54

Post by st26 »

BooneJS wrote: post #47

In the beginning, a sea of discrete components made up a system. Investment in fab technology caused process nodes to shrink very 18 months so these discrete components gave way to the System-On-Chip where the board of chips was replaced by a single chip. Now physics is harder to overcome, the cost of development at the bleeding edge of technology is higher than ever, and the continued desire for larger and larger sy…

What is old is new again. We'll probably go in this direction for a decade or three, breaking things up. Then we'll go the other way again, integrating everything into one chip again.

Re: AMD Tackles Coming “Chiplet” Revolution With New Chip Network Scheme

#55

Post by st26 »

sixdimensional wrote: post #30

I wonder if FPGAs could be a node too. That would allow us to mix programmable, highly parallel analog modeled acceleration onto the same high speed / direct connect bus as all the other fixed, traditional computing components. I really like the approach AMD is suggesting here, treating it like nodes on a network.

Hypothetically, yes. But FPGA's are very area-hungry; a big powerful one isn't going to fit nicely into a modestly sized package along with lots of other chips.

Re: AMD Tackles Coming “Chiplet” Revolution With New Chip Network Scheme

#56

Post by st26 »

gigatexal wrote: post #2

Any hardware gurus out there care to tak about how this helps? I guess having a flat pool of heterogenous resources is nice. As long as there’s a decent SDK that abstracts the hard stuff away I’m all for it.

A more modular package brings a variety of benefits. Small chips are cheaper per unit area, because yields are higher. Reuse in different products can also lower development costs. Different IP can live on the most appropriate technology node- mature & cheap, new & fast, etc. IP can be developed on different schedules. IP from completely different companies can be integrated more easily. (see the intel-AMD partnership, it's "chiplet")

It's really not that complicated an idea- modular packages are more flexible! What's new is making it work within a compelling power, price, and performance envelope.

Re: AMD Tackles Coming “Chiplet” Revolution With New Chip Network Scheme

#57

Post by davrosthedalek »

frozenport wrote: post #45
Quequau wrote: post #35

Earlier quoted context omitted.

I can't afford Intel's high-end stuff. That's why I'm looking at AMD.

Really the network is the least expensive part. To get IO that can saturate a 10G costs around 20k, while the infiniband card sets you back less than 4k. Now you're talking about 100G, which will go faster, you could easily be looking at a 500k box of ssds.

Wait, what? 10G is 1.2 GByte/s, you can get that from a single SSD easily. 100G is 12 GByte/s, so 5 consumer-level ssds. Squeezing 12 GByte/s over the buses twice might be tricky, but certainly not a 500k problem.

Re: AMD Tackles Coming “Chiplet” Revolution With New Chip Network Scheme

#58

Post by zitterbewegung »

kdmytro wrote: post #42
zitterbewegung wrote: post #17

Earlier quoted context omitted.

They also have a budget Ryzen that does the same thing but with their own Vega graphics. I am using one now for web development and distributed ledger development.

> ... and distributed ledger development. You are careful not to say "blockchain" :)

Yea, because the term keeps on being conflated. Blockchain means everything from cryptocurrencies to private ledger systems like hyperledger sawtooth.

Re: AMD Tackles Coming “Chiplet” Revolution With New Chip Network Scheme

#60

Post by paulmd »

st26 wrote: post #53
paulmd wrote: post #48

Earlier quoted context omitted.

> The advantage for AMD is that they've built a single design: the Zeppelin die. RyZen is simply one Zeppelin. Threadripper is two Zeppelins. And EPYC is four Zeppelins. While a popular meme, this is not actually true. Epyc is actually a totally different die, stepping B2 vs the B1 die used in Ryzen+TR. https://en.wikichip.org/wiki/amd/ryzen_7/1800x https://en.wikichip.org/wiki/amd/epyc/7601 The 2700X is actually on…

Steppings are minor revisions, perhaps analogous to a kernel patch revision. So they do have to manufacture B2 die and B1 die and they are not interchangeable- but they are 99.999% identical.

It still means these dies have to be fabbed and binned separately. Epyc and Ryzen are different dies and not interchangeable, they are not "the same die used across the whole lineup".
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