51–60 of 113 posts
"Price: Arm, Leg" ... hard to miss the sarcasm.
Arria 10 FPGA is kind of mid range, I think they go around for 500 bucks , you can buy the dev board for 5K ( https://www.altera.com/products/boards_and_kits/dev-kits/alt... )
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We get paid bank, there are very few of us, and the older you get and the more horror stories you've seen the more you're worth (unlike software). Gray in your beard is a feature, not a flaw. You're responsible for time critical and/or DSP things that are critical system architecture, and will never be outsourced (it's key IP, you'd be stupid to outsource that). Don't let anyone know, we have a good thing going on.
How do you define "bank"?
EDIT: You may also hear the phrase "making bank" to mean making (earning, not printing) a lot of money.
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The FPGAs are programmable using OpenCL. That counts? https://www.altera.com/products/design-software/embedded-sof...
I don't know if I'd call that programmable, isn't it just sequencing work to predefined logic blocks? Can you do things that were not contemplated by the opencl design?
Earlier quoted context omitted.
Arria 10 FPGA is kind of mid range, I think they go around for 500 bucks , you can buy the dev board for 5K ( https://www.altera.com/products/boards_and_kits/dev-kits/alt... )
Why are dev boards that much more expensive in general? I can't believe that it costs 10x as much to "just" put the chip on a pcie board.
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> increasingly smaller number and expensive lot of folks. There is this sentiment on HN that people in EE/embedded space don't really get paid well (compared to the average Javascript-slinging frontend dev). Is this not true for HDL folks?
We get paid bank, there are very few of us, and the older you get and the more horror stories you've seen the more you're worth (unlike software). Gray in your beard is a feature, not a flaw. You're responsible for time critical and/or DSP things that are critical system architecture, and will never be outsourced (it's key IP, you'd be stupid to outsource that). Don't let anyone know, we have a good thing going on.
Earlier quoted context omitted.
Getting paid bank means getting paid a lot of money. EDIT: You may also hear the phrase "making bank" to mean making (earning, not printing) a lot of money.
I think they were probably looking for a salary range.
Earlier quoted context omitted.
We get paid bank, there are very few of us, and the older you get and the more horror stories you've seen the more you're worth (unlike software). Gray in your beard is a feature, not a flaw. You're responsible for time critical and/or DSP things that are critical system architecture, and will never be outsourced (it's key IP, you'd be stupid to outsource that). Don't let anyone know, we have a good thing going on.
How do you define "bank"?
Earlier quoted context omitted.
> increasingly smaller number and expensive lot of folks. There is this sentiment on HN that people in EE/embedded space don't really get paid well (compared to the average Javascript-slinging frontend dev). Is this not true for HDL folks?
I work on operating systems, which is similarly niche (but probably overall easier to learn and low risk vs fabbing ASICs) an it is very bi-modal. Sr. circuit designers can write their ticket, but you have a lot of warm bodies surrounding them at large companies.
One stark flailure of the Altera acquisition is there has been little by way of tool chain integration. This is a CPU with a bag on the side, and that bag needs people that write HDL and understand computer architecture to make good use of. It's not really a harsh critique, but a warning that the lower you go is an increasingly smaller number and expensive lot of folks. Intel's marketing arm can't distort that realit…
Have a look at nGraph: http://ngraph.nervanasys.com/docs/latest/optimize/generic.ht...
Co-design for hardware+software is tough, for sure. But the reality is that hardware has to be present to build the software on top of it. People need something to play with. So the "bag on the side" of FPGAs here is kind of like Lego blocks for cache / acceleration. If you are running a DNN for inference, for example, cache is usually your bottleneck. Rent GPUs to train the model, figure out your bottleneck, and build your own isolated and local system for the "expensive lot of folks" to create the valuable IP.