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Test Results for AMD Zen 5

agner.org

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Re: Test Results for AMD Zen 5

#41

Post by Dylan16807 »

pbsd wrote: post #12

Vector ALU instruction latencies are understandably listed as 2 and higher, but this is not strictly the case. From AMD's Zen 5 optimization manual [1], we have The floating point schedulers have a slow region, in the oldest entries of a scheduler and only when the scheduler is full. If an operation is in the slow region and it is dependent on a 1-cycle latency operation, it will see a 1 cycle latency penalty. There…

So if you fill up the scheduler with a long line of dependent instructions, you experience a significant slowdown? I wonder why they decided to make it do that instead of limiting size/fill by a bit. What all the tradeoffs were.

Re: Test Results for AMD Zen 5

#42

Post by JackYoustra »

Tuna-Fish wrote: post #10
eigenform wrote: post #2

This reminds me: has anyone ever figured out why Zen 3 was missing memory renaming, but it came back in Zen 4 and Zen 5?

AMD had two leapfrogging CPU design teams. Memory renaming was added by the team that did Zen2, presumably the Zen3 team couldn't import it in time for some reason.

Any writeups on why they chose this system, whether its still used today, etc? I'm completely unfamiliar with this style of management.

Re: Test Results for AMD Zen 5

#43

Post by qwertox »

At the bottom of the post is a link to a PDF of "The microarchitecture of Intel, AMD, and VIA CPUs - An optimization guide for assembly programmers and compiler makers" [0]

You might want to download it and just take a look at it so you know that this content exists.

[0] https://www.agner.org/optimize/microarchitecture.pdf

Re: Test Results for AMD Zen 5

#44

Post by tw1984 »

monster_truck wrote: post #33

This matches my experience with Zen in basically any generation. Once you've used all of the tricks and exhausted all of the memory and storage bandwidth, you'll still have compute left. It's often faster to use one less core than you hit constraints at so that the processor can juggle them between cores to balance the thermal load as opposed to trying to keep it completely saturated.

this is very interesting. any chance you have more concrete stats or results?

thanks

Re: Test Results for AMD Zen 5

#45

Post by Sesse__ »

monster_truck wrote: post #33

This matches my experience with Zen in basically any generation. Once you've used all of the tricks and exhausted all of the memory and storage bandwidth, you'll still have compute left. It's often faster to use one less core than you hit constraints at so that the processor can juggle them between cores to balance the thermal load as opposed to trying to keep it completely saturated.

I had real code that ran with IPC > 6 on Zen 3; I think that's the first time I've seen a modern CPU _really_ be ALU-bound. :-) But it was very unusual, and when I vectorized it, it ran completely different.

Re: Test Results for AMD Zen 5

#47

Post by menaerus »

ryao wrote: post #21
ashvardanian wrote: post #5

> All vector units have full 512 bits capabilities except for memory writes. A 512-bit vector write instruction is executed as two 256-bit writes. That sounds like a weird design choice. Curious if this will affect memcpy-heavy workloads. Writes aside, Zen5 is taking much longer to roll out than I thought, and some of AMD's positioning is (almost expectedly) misleading, especially around AI. AMD's website claims Zen5…

AMD CPUs tend to have more memory bandwidth than Intel CPUs and inference is CPU bound, so their claim seems accurate to me. Whether the core does a 512-bit write in 1 cycle or 2 because it is two 256-bit writes is immaterial. Memory bandwidth is bottlenecked by 64GB/sec per CCX. You need to use cores from multiple CCXs to get full bandwidth. That said, the EYPC 9175F has 614.4GB/sec memory bandwidth and should be ab…

Interesting design. 16 CCDs / 16 CCXs / 16 cores. 1 core per each CCD. 1 CCX per each CCD. With 512MB of L3 cache this CPU should be able to use ~all of its ~10 TB/s of L3 MBW out of the box.

How much is it going to cost you to build the box?

Re: Test Results for AMD Zen 5

#48

Post by menaerus »

crest wrote: post #29
varispeed wrote: post #18

Is it better than M4? If a laptop will need to be plugged in to deliver full performance, whilst blasting fans at full throttle, what is the point? (apart from server / workstation use, where you don't like MacOS or need different OS)

Depends on your usecase. For a thin 14" laptop an M4 is probably the closer sweet spot, but for CPU heavy workloads Apple doesn't offer anything comparable to Threadripper or EPYC (lots of fast cores, enough memory and I/O bandwidth).

Actually Apple M design can hit ~100GB/s of MBW with a single core. Something that many other (or basically none?) CPUs of the same range couldn't.

Re: Test Results for AMD Zen 5

#49

Post by throwaway81523 »

JackYoustra wrote: post #42
Tuna-Fish wrote: post #10

Earlier quoted context omitted.

AMD had two leapfrogging CPU design teams. Memory renaming was added by the team that did Zen2, presumably the Zen3 team couldn't import it in time for some reason.

Any writeups on why they chose this system, whether its still used today, etc? I'm completely unfamiliar with this style of management.

Dunno about writeups but I've worked in that system. Basically the product lifecycle is longer than one product generation. So you get to stay with it through the development, test/release, and maintenance phases, which are arranged to be 2 release cycles. It didn't seem paradoxical or anything. It just made sense.

Re: Test Results for AMD Zen 5

#50

Post by ashvardanian »

reitzensteinm wrote: post #37
ashvardanian wrote: post #5

> All vector units have full 512 bits capabilities except for memory writes. A 512-bit vector write instruction is executed as two 256-bit writes. That sounds like a weird design choice. Curious if this will affect memcpy-heavy workloads. Writes aside, Zen5 is taking much longer to roll out than I thought, and some of AMD's positioning is (almost expectedly) misleading, especially around AI. AMD's website claims Zen5…

This is a misreading of their website. On the left, they compare the EPYC 9965 (launched 10/10/24) with the Xeon Platinum 8280 (launched Q2 '19) and make a TCO argument for replacing outdated Intel servers with AMD. On the right, they compare the EPYC 9965 (launched 10/10/24) with the Xeon Platinum 8592+ (launched Q4 23), a like for like comparison against Intel's competition at launch. The argument is essentially in…

It’s true that they compare to different Intel CPUs in different parts of the webpage, and I don’t always understand the intentions behind those comparisons.

Still, if you decode the unreadable footnotes 2 & 3 in the bottom of the page - a few things stand out: avoiding AMX, using CPUs with different core-counts & costs, and even running on a different Linux kernel version, which may affect scheduling…

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