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TSMC 2nm Process Disclosure – How Does It Measure Up?

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Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#41

Post by mlyle »

zozbot234 wrote: post #26
adgjlsfhk1 wrote: post #22

Earlier quoted context omitted.

Riscv doesn't need smaller nm. It just needs someone to actually design and release a good core design. 14nm (or 4 or anything in between) is perfectly suffient to make a Riscv chip 10x faster than any Riscv that currently exist.

14nm or so is kind of a sweet spot for general purpose chip design right now, because later nodes turn out to have higher overall per-transistor cost despite the improvement in density and area. Of course this may well change over time as even finer production nodes get developed and the existing nodes then move closer to the trailing edge.

Of course, on the opposite side: if you have higher Fmax and lower power, you need fewer transistors to get the same characteristics for end users.

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#42

Post by fngjdflmdflg »

wuschel wrote: post #32
adgjlsfhk1 wrote: post #22

Earlier quoted context omitted.

Riscv doesn't need smaller nm. It just needs someone to actually design and release a good core design. 14nm (or 4 or anything in between) is perfectly suffient to make a Riscv chip 10x faster than any Riscv that currently exist.

What do you tbink is holding RiscV core design back? Is it the IP situation?

Not a hardware person but I read in an interview with Jim Keller that ISA itself doesn't matter that much for performance.

>[Arguing about instruction sets] is a very sad story. It's not even a couple of dozen [op-codes] - 80% of core execution is only six instructions - you know, load, store, add, subtract, compare and branch. With those you have pretty much covered it. If you're writing in Perl or something, maybe call and return are more important than compare and branch. But instruction sets only matter a little bit - you can lose 10%, or 20%, [of performance] because you're missing instructions.[0]

I've cited this article a few times already (and seen others cite it) so if this is incorrect I hope someone could correct me here. (I have to assume that you also need some sort of SIMD/Vector these days, which RVA23 has anyway, but aside from that.)

I've also read that you can port CPU cores to a different ISAs pretty easily which is what PA Semi did when Apple bought them (M1 devs). So what seems to be missing is for a bunch of senior CPU developers who worked at AMD, Intel, PA Semi/Apple or ARM to just make one for RISC-V. Not sure if that is what you meant by IP here. Tenstorrent could be one such group, and they are building RISC-V CPUs, but their focus seems to be split between that and AI accelerators. China is another good candidate.

[0] https://www.anandtech.com/show/16762/an-anandtech-interview-...

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#43

Post by Pet_Ant »

magicalhippo wrote: post #13
hcfman wrote: post #10

Super interesting. Now what we really need is for Raspberry Pi to make a 2nm version so that the power usage becomes more acceptable for Wildlife and biodiversity use cases. Please, please Raspberry Pi, also make a 2nm version Actually, I think it's broadcom I need to ask that from isn't it ? (Although then I think it would almost become a Jetson) Please please NVidia make a 1nm Jetson, the planet needs you to.

The current Pi 5 is on a 16nm node[1], down from 28nm for the Pi 4. So, far off needing a bleeding edge node[2] to see further improvements. [1]: https://chipwise.tech/our-portfolio/raspberry-pi-5/ [2]: https://www.tsmc.com/english/dedicatedFoundry/technology/log...

For reference GlobalFoundries (who AMD left because they weren't willing to adopt EUV which is needed for cutting edge geometries) goes up to 12nm, so that means there is still room for Pis to improve before hitting the expensive stuff.

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#44

Post by Aperocky »

dannyw wrote: post #14
thiago_fm wrote: post #12

Is there an advantage on going 2nm given the costs? Maybe somebody can clearly answer this here on HN, I love this subject! It's interesting how the whole valuation of TSMC(and some from NVidia) are aligned by their current advantage on the 3nm process. Intel on 18A is literally TSMC's 3nm process + backside power delivery, which means more power efficiency, performance also less heat. It's definitely what they need…

For datacenters and especially hyperscalers, the power and cooling bill is a huge part of the TCO. You make somewhat more power efficient chips, you get to sell it for a lot more. Your chips are inefficient, and you won’t be able to sell to a hyperscaler even for $0. The latter is the position Intel is quickly arriving at for DC; Epycs are much more efficient and Intel’s wildly slashing prices. — For Apple, A-series…

> That said, Apple’s strict fascination with always jumping to the latest node, even when it seems premature, puzzles me from the outside.

As a user of M1, M2 and M4, that's why I've chose Apple.

I would have gladly jumped to any laptop that supports Linux with similar power and battery life and weight/build, unfortunately that computer does not exist.

Is it time to call on garmin to make a computer? They've beat apple on the watch. I have faith in them.

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#45

Post by EncomLab »

fngjdflmdflg wrote: post #42
wuschel wrote: post #32

Earlier quoted context omitted.

What do you tbink is holding RiscV core design back? Is it the IP situation?

Not a hardware person but I read in an interview with Jim Keller that ISA itself doesn't matter that much for performance. >[Arguing about instruction sets] is a very sad story. It's not even a couple of dozen [op-codes] - 80% of core execution is only six instructions - you know, load, store, add, subtract, compare and branch. With those you have pretty much covered it. If you're writing in Perl or something, maybe…

Keller is just a god tier hardware guy - his ability to leverage deep understanding and then explain incredibly complex issues in a few sentences is incredible. Intel shot themselves in the foot when they let him go.

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#47

Post by tarnith »

zozbot234 wrote: post #39
thunderbird120 wrote: post #38

Earlier quoted context omitted.

If that were totally true you would expect to see more or less uniform ratios of HP/HD cells mixes across different product types, but that's very much not the case. Dennard scaling may be dying but it's not dead yet. You can still sacrifice efficiency to gain performance. It's not zero sum.

What product types do you have in mind exactly? Even big server chips now use a huge fraction of their area for power-sipping "efficiency core" designs that wouldn't be out of place in a mobile chip. Power is king.

AMD Zen5?

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#48

Post by topspin »

fngjdflmdflg wrote: post #42
wuschel wrote: post #32

Earlier quoted context omitted.

What do you tbink is holding RiscV core design back? Is it the IP situation?

Not a hardware person but I read in an interview with Jim Keller that ISA itself doesn't matter that much for performance. >[Arguing about instruction sets] is a very sad story. It's not even a couple of dozen [op-codes] - 80% of core execution is only six instructions - you know, load, store, add, subtract, compare and branch. With those you have pretty much covered it. If you're writing in Perl or something, maybe…

Most of the same was said by Jim in this live interview: https://www.youtube.com/watch?v=rfFuTgnvwgs

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#49

Post by topspin »

wuschel wrote: post #32
adgjlsfhk1 wrote: post #22

Earlier quoted context omitted.

Riscv doesn't need smaller nm. It just needs someone to actually design and release a good core design. 14nm (or 4 or anything in between) is perfectly suffient to make a Riscv chip 10x faster than any Riscv that currently exist.

What do you tbink is holding RiscV core design back? Is it the IP situation?

The RISC-V core designs that have emerged so far don't have nearly the amount of silicon dedicated to optimizing IPC as one sees in ARM, x86 and others: predictors, sophisticated caches, complex instruction dispatch, deep pipelines, etc. That stuff isn't provided with the RISC-V core designs you get for free or license at low cost, because it's fabulously expensive to develop, tied to the ISA and core designs for which it is created, and jealously guarded through IP law.

Will RISC-V get there eventually? People like Jim Keller are building companies around that goal. However, it will likely take years, at least, for RISC-V to approach parity.

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#50

Post by distances »

zozbot234 wrote: post #26
adgjlsfhk1 wrote: post #22

Earlier quoted context omitted.

Riscv doesn't need smaller nm. It just needs someone to actually design and release a good core design. 14nm (or 4 or anything in between) is perfectly suffient to make a Riscv chip 10x faster than any Riscv that currently exist.

14nm or so is kind of a sweet spot for general purpose chip design right now, because later nodes turn out to have higher overall per-transistor cost despite the improvement in density and area. Of course this may well change over time as even finer production nodes get developed and the existing nodes then move closer to the trailing edge.

The article linked in another comment pointed out that cost per transistor keeps falling, and it's just the fast increasing fixed costs that make it seem otherwise.

https://semianalysis.com/2022/07/24/the-dark-side-of-the-sem...

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