41–50 of 159 posts
Of course, there's always the "make a 4 core chip. If one core doesn't work, sell it as a 3 core chip. And so on."
Are we moving this way because bigger chips with many cores have worse yields? so the answer is to make lots of little chips and fuse then together?
I think they do it using identical chips but I guess there's no real reason you couldn't have different chips connected in one wafer. Expensive though!
The best chiplet interconnect may turn out to be no interconnect at all. Wafer scale integration [1] has come up periodically over the years. In short, just make a physically larger integrated circuit, potentially as large as the entire wafer -- like a foot across. As I understand it, there's no particular technical hurdle, and indeed the progress with self-healing and self-testing designs with redundancy to improve…
To clarify and contextualize a bit what you're saying: The one big obstacle in creating larger chips is defects. There's just a statistical chance of there being a defect on any given surface area of the wafer, defect which generally breaks the chip that occupies that area of the wafer. So historically, the approach was to make more smaller chips and trash those chips on the wafer affected by defects. Then came the "…
The best chiplet interconnect may turn out to be no interconnect at all. Wafer scale integration [1] has come up periodically over the years. In short, just make a physically larger integrated circuit, potentially as large as the entire wafer -- like a foot across. As I understand it, there's no particular technical hurdle, and indeed the progress with self-healing and self-testing designs with redundancy to improve…
The M1 Ultra is fabricated as a single chip. The 12900K is fabricated as a single chip and is still a quarter the size of the M1 Ultra. Ryzen 3 puts 8 cores on a CCX instead of four because DDR memory controllers don't have infinite memory bandwidth (contrary to AMD's wishful nomenclature) and make shitty interconnects between banks of L3. Chiplets are valid strategies that are going to be used in the future but ther…
> The M1 Ultra is fabricated as a single chip. I'm curious how much the M1 Ultra costs. It's such a massive single piece of glass I'd guess it's $1,200+. If that's the case it doesn't make sense to compare the M1 Ultra to $500 CPUs from Intel and AMD.
The M1 Ultra is fabricated as a single chip. The 12900K is fabricated as a single chip and is still a quarter the size of the M1 Ultra. Ryzen 3 puts 8 cores on a CCX instead of four because DDR memory controllers don't have infinite memory bandwidth (contrary to AMD's wishful nomenclature) and make shitty interconnects between banks of L3. Chiplets are valid strategies that are going to be used in the future but ther…
> The M1 Ultra is fabricated as a single chip. I'm curious how much the M1 Ultra costs. It's such a massive single piece of glass I'd guess it's $1,200+. If that's the case it doesn't make sense to compare the M1 Ultra to $500 CPUs from Intel and AMD.
The best chiplet interconnect may turn out to be no interconnect at all. Wafer scale integration [1] has come up periodically over the years. In short, just make a physically larger integrated circuit, potentially as large as the entire wafer -- like a foot across. As I understand it, there's no particular technical hurdle, and indeed the progress with self-healing and self-testing designs with redundancy to improve…
To clarify and contextualize a bit what you're saying: The one big obstacle in creating larger chips is defects. There's just a statistical chance of there being a defect on any given surface area of the wafer, defect which generally breaks the chip that occupies that area of the wafer. So historically, the approach was to make more smaller chips and trash those chips on the wafer affected by defects. Then came the "…
This is already happening for almost all modern chips manufactured in the last 10+ years. DRAM chips have extra rows/cols. Even Intel CPUs have redundant cache lines, internal bus lines and other redundant critical parts, which are burned-in during initial chip testing.
I'm embarrassed to admit I still don't quite understand what a chiplet is, would be very grateful for your input here. If a thread can run on multiple chiplets then this is awesome and seems like a solution. If one thread == one chiplet, then*: - a chiplet is equivalent to a core, except with speedier connections to other cores? - this isn't a solution, we're 15 years into cores and single-threaded performance is sti…
A chiplet is a full-fledged CPU with many cores on it. The term is used when multiple of these chips are stitched together with a high speed interconnect and plugged into the single socket on your motherboard. If you ripped the lid off a Ryzen "chip", you would see multiple CPU dies underneath for the high end models.
Examples at the Wikipedia article: https://en.wikipedia.org/wiki/Multi-chip_module
"Single-Chip Processors Have Reached Their Limits Announcements from XYZ and ABC prove that chiplets are the future, but interconnects remain a battleground" This could easily have been written 10 years ago, and I bet someone will write it in 10 years again. We need these really big chips with their big powerful cores because the nature the computing we do only changes very slowly towards being distributed and parall…
You're implying you can't put big powerful cores on chiplets but that's not true at all.
So if you want better aggregate performance, more cores has been the plan for a decade+ now.
FLOP/s per core or whatever other metric you choose to use.
Previously it was possible to get 20-50% or more performance improvements even year to year for a core.