> But the Ryzen 5000 mobile chips really don't look bad at all in comparison, and a 5nm version of those would level the field.
Not look too bad best to say.
Even if we add a one node advantage, we still have a ~15 watt chip making 20W-30W chips sweat.
If you downclock Zen 3 to match 15W TDP, you may well get M1 beating it by double digit margin.
M1 is simply a way more efficient chip than any X86 chip can be because of 40 years of architectural advantage.
- latest x86 chips have patently gigantic decoders metastasising into backend. They are very tightly coupled to pretty much every other piece of logic.
- x86 memory model, and blockage behaviour costing huge transistor count to work around
- better SMP efficiency because of laxer memory model, and SMP logic being deeper integrated into cores, rather than being an afterthought
- generally better register utilisation, at lower transistor count, and the upstream software ecosystem historically having better understanding how to work with large register count
- X86 cores prefetch from both main memory, and in between caches is more expensive, and less efficient because it has to rely on more complex logic, and do more guesswork than in ARM.
The list can go on for a few more screens.
Remember. Even if M1 is a SoC, it still manages to beat Ryzen which barely have much besides cores, memory controller, PCIE, and USB. If you give a 1 node handycap to Ryzen, and only compare cores, you will still get M1 having almost 3 to 4 times advantage at performance per square mm.
It's really sad to see X86 development digging itself into a ditch with "40 years binary compatibility at any cost."
With all regards to Su Lisa, I believe they very much understand all that, but nevertheless still signed under the idea that X86 market will never go anywhere.
I believe it's trivial for both AMD, and Intel to easily slash X86 transistor counts, while increasing the performance by double digits if they can go in err of the X86 ISA convention on just the few most egregious anachronisms.