Hacker News Board Hacker News, browsed like a classic message board
Live data from Hacker News

A third world engineer responds to “RISC-V: They should have known better”

rvembedded.com

Post reply on HN
Print view View original

321–330 of 350 posts

Re: A third world engineer responds to “RISC-V: They should have known better”

#321

Post by hajile »

strenholme wrote: post #201
jackb4040 wrote: post #196

Earlier quoted context omitted.

It's fascinating to me what you're describing. That ISA prevalence basically comes down to the anarchy of the market, and theoretical differences in the actual design don't really factor in. Is this true? Can we analyse the reasons we expect RISC-V to have better performance, and possibly even extrapolate that to a theoretically even better ISA and skip over RISC-V entirely?

Getting RISC-V to have better performance is a matter of in-chip optimizations (caches, pipelines, etc.) and high quality performance oriented fabs. The dominance of x86 after the dot-com bubble popped shows that one can get incredible performance even from an ISA which is a hack on top of a hack on top of another hack. [1] In terms of a “theoretically even better ISA”, if anyone has any proposals, I would love to se…

> I will make one ISA propsal: x86_64 should have had 32 instead of 16 registers

APX proposes exactly this along with 3-register syntax and some other things.

There are two big issues IMO.

1. It will take at least 15 years before most software ships with this because unlike something like AVX where you typically just rewrite a small part of your code that needs AVX, APX requires a 100% rewrite to take advantage.

2. APX instructions require an additional byte each time you use them compared to current instructions. I think there are still savings to be found, but they won't be as big as it might seem at first.

Lack of serious incentive combined with decades-long rollout seems a recipe for non-adoption at a time when RISC chips offer these features now.

Re: A third world engineer responds to “RISC-V: They should have known better”

#322

Post by hajile »

TMWNN wrote: post #253
strenholme wrote: post #187

I believe there will come a day when RISC-V has comparable or better performance than ARM and x86_64. This is based on history: I remember when x86 performance compared to the DEC Alpha, PA-RISC, SPARC, etc. was a joke. There was a time when, if you wanted real performance, you needed to pony up $20,000-$50,000 for a workstation with a MIPS/PA-RISC/SPARC/Alpha/whatever processor. All these workstations smoked the x86…

>Right now, RISC-V is mainly being used in cheap embedded components. Considering that x86 and ARM also were made for cheap computing, until becoming the dominant high end processor, history tells us that the cheapest ISA is the one which will become the highest performance one. You surely mean "history tells us that the cheapest and largest-volume ISA is the one which will become the highest performance one". It's n…

Here's a good one.

Qualcomm beat ARM in court and reportedly pays 2-3% royalties where ARM was demanding 5-10% royalties.

Qualcomm's ARM license expires around 2028 with an option to extend to 2033 (for some amount of money). If Qualcomm is locked into ARM when renewal comes up, ARM is going to not only name the higher price, but likely charge even more to recover their lost revenue.

Qualcomm is already designing their own cores and ARM is charging them billions for the privilege. Increasing net profits 2-3% for simply doing the thing you are doing seems like a very easy choice. Increasing net profits 5-10% (maybe more) after the price hike seems like a fiduciary responsibility.

This isn't just talk either. Qualcomm already proposed a RISC-V Znew extension (nearly 300 pages of changes to make the ISA more like ARMv8). They bought Ventana (a company already done with their second very wide RISC-V design). They partnered with other companies to make Quintauris for promoting RISC-V too.

There's a non-zero chance we see a RISC-V design from Qualcomm before 2028 and I believe a near 100% certainty of a RISC-V design before 2033.

Re: A third world engineer responds to “RISC-V: They should have known better”

#323

Post by hajile »

bsder wrote: post #193
kazinator wrote: post #95

> He derives the case for the chip and then spends the rest of the article annoyed that the chip exists. This is almost satirical. His criticisms are entirely valid, because why can't the the thing that has a free spec and will likely dominate that space ... also be good too? Can't we have all the nice things?

Because the people driving the RISC-V ISA all care about delivering IP and not chips and, as such, only care about the high end portion of the market. The problem is that RISC-V is never going to win at the high end . RISC-V will never have as much money driving it forward as x86 and ARM. As such, the blocks and integration will always lag. The portion of the market which RISC-V could dominate is the low-end (you kno…

> The problem is that RISC-V is never going to win at the high end. RISC-V will never have as much money driving it forward as x86 and ARM. As such, the blocks and integration will always lag.

Qualcomm recently bought Ventana and are looking at paying ARM billions (in addition to their current billions) for the privilege of designing their own cores. They sit on the RISC-V consortium and made proposals like Znew.

We could be seeing a high-performance RISC-V release from Qualcomm quite soon (especially if they can simply swap out the ARM decode for RISC-V).

Re: A third world engineer responds to “RISC-V: They should have known better”

#324

Post by hajile »

teo_zero wrote: post #254
codedokode wrote: post #154

I disagree with some points in "RISC-V They Should Have Known Better". For example, author claims that saving and restoring all registers in interrupt handler takes too long. But this can be solved alternatively, for example: split register set for use in interrupt and normal code. Or simply add two register banks and allow switching between them (assuming interrupts are not re-enterable). But author claims that ARM…

> As for 3 instructions for array access, in a simple loop a compiler can convert index access to pointer increment. In such a simple loop where you access one field in each iteration, yes. If you happen to access more fields, or the same field in different arrays, then you have more pointers to increment.

If such an instruction is so obviously important, we'll see it start popping up as a custom instruction in some cores then it will get adopted as an official extension by other companies trying to stay competitive.

Re: A third world engineer responds to “RISC-V: They should have known better”

#325

Post by hajile »

Ericson2314 wrote: post #88

My perspective using Nix is that it's hardly worth standardizing ISAs. Recompiling software is easy and we should have a Cambrian explosion of different designs. This is especially good if one scopes out a family of ISAs that are ABI compatible such that one can compile down to a semi-pre-optimized portable IR, and just do the last bit per ISA.

Rewriting critical stuff like hand-written SIMD takes a long time (though not as long as it took ARM because ARM had to overcome everything being written in just one ISA). Even a decade in, there are still lots of low-hanging fruit in RISC-V compilation that is still being dealt with. There's quite a few really great talks about the progress here and I think we're going to continue to see major gains in RISC-V performance via compiler changes for quite a while longer.

Re: A third world engineer responds to “RISC-V: They should have known better”

#326

Post by hylaride »

RetroTechie wrote: post #314
hylaride wrote: post #304

Earlier quoted context omitted.

My understanding is that RISC-V needs both economies of scale AND chips that are manufactured at the bleeding edge fabs (smallest dies, etc) which is a lot more expensive. It's a chicken and egg problem as there's not (yet?) demand. The architectural limitations will remain until there's incentive to work on it. In many ways it's not much different than Linux was in the 1990s. It was cheap and useful, but often not a…

> RISC-V needs both economies of scale AND chips that are manufactured at the bleeding edge fabs (smallest dies, etc) which is a lot more expensive. It's a chicken and egg problem as there's not (yet?) demand Whatever leading-edge fab capacity (mostly TSMC) was available, is now tied up to supply the ongoing AI boom. And will remain so for the foreseeable future. Even if you'd have a RISC-V product for which demand/e…

It can be a demand problem. People/companies aren't going to spend the time optimizing (including compilers/code) if there's no payoff that's greater than the delta for an arm chip.

That being said, demand from and via China (which has a geopolitical case for wanting to see risc-v succeed) will probably end up being what drives it forward.

Re: A third world engineer responds to “RISC-V: They should have known better”

#327

Post by RetroTechie »

strenholme wrote: post #187

I believe there will come a day when RISC-V has comparable or better performance than ARM and x86_64. This is based on history: I remember when x86 performance compared to the DEC Alpha, PA-RISC, SPARC, etc. was a joke. There was a time when, if you wanted real performance, you needed to pony up $20,000-$50,000 for a workstation with a MIPS/PA-RISC/SPARC/Alpha/whatever processor. All these workstations smoked the x86…

You're on the right track. But imho it's about hitting a sweet spot in whatever the market wants @ a certain time. There's a lot of luck involved.

x86 hit that sweet spot: 8088/8086 performance nicely between much-weaker, memory constrained 8-bitters and too-expensive SPARK/MIPS/Alpha etc workstations. Then the BIOS situation opening the door for PC clone builders, Intel's good fabbing, and presto: x86 took off. People just bought PCs because economies of scale provided increasing bang/buck compared to other offerings.

ARM: grew steadily in embedded. Then "mobile" became big, ARM was objectively better than x86 there (battery! perf/W), and the market size provided huge $$ royalties that enabled ARM to hire top-talent engineers & improve their next designs. Leaving their competition in the dust. Steadily upping performance lead to things like ARM based laptops & servers.

RISC-V is largely riding the "open" wave. Which does translate into practical advantages like driving down product cost, software support improving fast due to the shared ecosystem, etc. But again: much luck involved - timing of its introduction, cheap FPGA boards becoming available to developers & students, the ISA itself being fairly sane (even called "boring", which is good in this context), its modularity positioning it across a wide range of markets, coumtries like China looking for tech-independence, etc.

This much like ~1850's industrialisation in Britain: ANY one of the factors missing could have lead to failure.

Personally I have high expectations for RISC-V. But regardless how it'll pan out: it's well past critical mass, so it's here to stay.

Re: A third world engineer responds to “RISC-V: They should have known better”

#328

Post by Dylan16807 »

bigcat12345678 wrote: post #40
HawtAds wrote: post #4

I love the article, it's a breath of fresh air compared to the usual bay area centric takes. However there's just one issue: > The students I want to teach are in the same position, and so are the ones in Nigeria and Bangladesh It does not take $60 to ship small sub $1 chips from Asia to Nigeria/Bangladesh. These two countries are all on global trade routes (both supply and demand) and the expensive last mile deliver…

This is a bay area centric take on a non bay area centric take. The typical bay area centric take has the following vibe: 1. I am among the group of most open minded people 2. I admit mistakes, but I don't change my view, that means I may make the same mistakes next time on a different concrete cases 3. Morally I am among the least corrupted 4. I work for the moderately morally questionable firms with nice paychecks,…

Being generically insulting without addressing the topic is really unhelpful even if you're right about the specific thing that triggered the insult!

Re: A third world engineer responds to “RISC-V: They should have known better”

#329

Post by daemin »

muyuu wrote: post #160
andai wrote: post #146

Earlier quoted context omitted.

Interesting. So I've seen a lot of reviews of RISC-V machines and they seem to be a decade or more behind in terms of performance. I always thought that was a case of "the tech is still catching up",[0] but it sounds like there are fundamental issues that prevent performant implementations? If so... I heard China was investing heavily in RISC-V, which implies that either they're going to have to settle for permanentl…

the main problem with RISC-V is also the main selling point: there is no single owner company behind steering development and making sweeping decisions how will that pan out over the long term is really unclear and the reality is performance is actually catching up quickly

What I see is that you'll get low end chips for embedded applications, because you tend to specifically build and compile programs for things as small as that. You'll also get the large sever and massive super-computer scale systems, because yet again you'll compile code specifically for those systems.

What you're less likely to get is the consumer level PC and Laptop systems, as you'll need one large company to set the standard and others to adhere to it. So you could feasibly compile a program for a certain level of RISCV chip and have it run on many vendors processors. As it is there's several companies trying to push ARM for some sort of high end consumer PCs/Laptops but they all require different OSes and the chips aren't equivalent, so you have to compile software separately for those different platforms.

Re: A third world engineer responds to “RISC-V: They should have known better”

#330

Post by Dylan16807 »

initramfs wrote: post #63
Conan_Kudo wrote: post #56

Earlier quoted context omitted.

There are 386 and 486 open source reimplementations in Verilog (see z386 and z486). As far as I know, existing commercial 386/486 chips still manufactured (yes they exist!) are descendants of Cyrix work, not Intel or AMD. Consequently, VIA may be contractually holding those back rather than Intel/AMD doing anything there.

Thanks for that information! I have been interested in getting x86 produced in smaller nanometer (e.g. https://ei2030.github.io/FemtoTX/#about Edit: It also appears Nvidia might also have an x86 license: https://www.nvidia.com/en-us/drivers/uli-m6117c/ Also, https://www.tomshardware.com/pc-components/cpus/intel-licens... (Caveat: The startup is acquainted with the Intel CEO, so it's rare for them to grant the x86 lic…

x86_64 is itself well over 20 years old. You don't have to pay for it. And at this point SSE4 is on the verge of escaping patents, so a new startup might as well aim for that level. AVX is where you might run into patent fuss, but AVX isn't particularly important.
Post reply on HN