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A third world engineer responds to “RISC-V: They should have known better”

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Re: A third world engineer responds to “RISC-V: They should have known better”

#251

Post by TMWNN »

MrBuddyCasino wrote: post #234
ndiddy wrote: post #66

I think he's kind of speaking past the original author. The original piece is basically about how the author doesn't think that RISC-V will take off outside embedded, because of some design decisions that lead to poor performance compared to ARM64 and because so much of the ISA being optional means that there's too much fragmentation to make binary distribution feasible. Meanwhile, this piece is mainly about how RISC…

> I think he's kind of speaking past the original author. Thats being generous. He is spinning this into a 3rd world / 1st world social justice story, while ignoring the technical points dmitry made.

I didn't get that impression. He talks about T&T (and places like that)'s inability to cheaply obtain components, but that's not the main point of his post

Re: A third world engineer responds to “RISC-V: They should have known better”

#252

Post by genxy »

TMWNN wrote: post #251
MrBuddyCasino wrote: post #234

Earlier quoted context omitted.

> I think he's kind of speaking past the original author. Thats being generous. He is spinning this into a 3rd world / 1st world social justice story, while ignoring the technical points dmitry made.

I didn't get that impression. He talks about T&T (and places like that)'s inability to cheaply obtain components, but that's not the main point of his post

Parent wanted to drop some anti-woke whistles because the author is black. Engineer from T&T makes a sound economic argument for the RISC-V ecosystem and suddenly it is "social justice". F that.

Re: A third world engineer responds to “RISC-V: They should have known better”

#253

Post by TMWNN »

strenholme wrote: post #187

I believe there will come a day when RISC-V has comparable or better performance than ARM and x86_64. This is based on history: I remember when x86 performance compared to the DEC Alpha, PA-RISC, SPARC, etc. was a joke. There was a time when, if you wanted real performance, you needed to pony up $20,000-$50,000 for a workstation with a MIPS/PA-RISC/SPARC/Alpha/whatever processor. All these workstations smoked the x86…

>Right now, RISC-V is mainly being used in cheap embedded components. Considering that x86 and ARM also were made for cheap computing, until becoming the dominant high end processor, history tells us that the cheapest ISA is the one which will become the highest performance one.

You surely mean "history tells us that the cheapest and largest-volume ISA is the one which will become the highest performance one".

It's not "RISC" having reached x86 levels; it's ARM variants. They did so with volume that for the first time in modern computing massively exceeded x86's. Apple's PA Semi acquisition has resulted in wizardry, but that wizardry would not have been possible without the massive volumes TSMC enjoys.

In any case, I'm not convinced that the above is sufficient; there has to be some level of technical superiority (or at least reasonably equal-level) as well. Otherwise, some inexpensive microcontroller that is manufactured at 100X the volume of x86 would have taken off. Does RISC-V have enough "goodness" in its design? I do not know.

Re: A third world engineer responds to “RISC-V: They should have known better”

#254

Post by teo_zero »

codedokode wrote: post #154

I disagree with some points in "RISC-V They Should Have Known Better". For example, author claims that saving and restoring all registers in interrupt handler takes too long. But this can be solved alternatively, for example: split register set for use in interrupt and normal code. Or simply add two register banks and allow switching between them (assuming interrupts are not re-enterable). But author claims that ARM…

> As for 3 instructions for array access, in a simple loop a compiler can convert index access to pointer increment.

In such a simple loop where you access one field in each iteration, yes. If you happen to access more fields, or the same field in different arrays, then you have more pointers to increment.

Re: A third world engineer responds to “RISC-V: They should have known better”

#255

Post by TMWNN »

overfeed wrote: post #181
bonoboTP wrote: post #171

Earlier quoted context omitted.

It's Global South now. A Global South embedded engineer.

Both the old and new forms are clumsy approximations; Trinidad & Tobago is (are?) in the northern hemisphere.

It's not darkest Africa, or Haiti, but it is sufficiently outside the normal trade routes to not have routine, inexpensive access to components that most of us here take for granted.

Re: A third world engineer responds to “RISC-V: They should have known better”

#256

Post by rurban »

HexDecOctBin wrote: post #248
rurban wrote: post #237

Earlier quoted context omitted.

It's not just Western shipping parts. You can buy cheap Indian parts, and have the very, same insane shipping costs as with "Western" parts. Ie a 2€ part from India will still cost 25€, whilst the 2€ part from China will cost 2-4€

Why is that? Is it simply a matter of scale (not enough shipping containers leaving from India to Trinidad and Tobago)?

In case of the China -> Europe and US routes it's certainly that the air fright traffic is heavily optimized and subsidized by China.

From India obviously not, so you have to pay normal shipping costs.

Re: A third world engineer responds to “RISC-V: They should have known better”

#257

Post by teo_zero »

avmich wrote: post #12

To me it feels like the difference in positions is "this could be made better" vs. "but this is already so much better than before". Both are right. Maybe I'm missing something important so far...

> the difference in positions is "this could be made better" vs. "but this is already so much better than before"

I would say "this could be technically better" vs. "this is already economically better than anything else"

Re: A third world engineer responds to “RISC-V: They should have known better”

#258

Post by bsder »

andai wrote: post #146
ndiddy wrote: post #66

I think he's kind of speaking past the original author. The original piece is basically about how the author doesn't think that RISC-V will take off outside embedded, because of some design decisions that lead to poor performance compared to ARM64 and because so much of the ISA being optional means that there's too much fragmentation to make binary distribution feasible. Meanwhile, this piece is mainly about how RISC…

Interesting. So I've seen a lot of reviews of RISC-V machines and they seem to be a decade or more behind in terms of performance. I always thought that was a case of "the tech is still catching up",[0] but it sounds like there are fundamental issues that prevent performant implementations? If so... I heard China was investing heavily in RISC-V, which implies that either they're going to have to settle for permanentl…

> I always thought that was a case of "the tech is still catching up",[0] but it sounds like there are fundamental issues that prevent performant implementations?

Yes, the fundamental problem is the fact that everybody involved in RISC-V wants to sell IP instead of a chip.

The problem with the RISC-V chips in non-embedded contexts (ie desktop or server) has absolutely nothing to do with the instruction set architecture (not entirely true but a really good first approximation). The problem is that performance is strongly dependent upon your high speed interfaces--memory, graphics, PCI, etc. And those blocks need to be strongly integrated in with your CPU interfaces.

However, if you buy a whole bunch of IP blocks and then just wire them together, your performance is going to be sub-par. And this is what every single RISC-V chip that I know of currently is.

It's not beyond someone to sit down and do the required integration like Apple did for ARM. There's just insufficient money in it so nobody is going to expend the engineers.

Re: A third world engineer responds to “RISC-V: They should have known better”

#259

Post by crote »

rasz wrote: post #220
kreelman wrote: post #215

Earlier quoted context omitted.

Here's the CH32v003, https://github.com/openwch/ch32v003 These are pretty low end and are fairly available at low cost. Here's a youtube of someone talking through some of the the CH32 boards, https://www.youtube.com/watch?v=Kss6WQvJbRs He talks about them being the "10c/chip" chip. Then, there is the CH32v303 https://www.wch-ic.com/products/CH32V303.html , which is the lower end of the chips that support minimal flo…

CH32v303 costs more than much more capable ARM based RP2354A

The "much more capable" is debatable. The RP2000 series is quite disappointing IO-wise: no timers, barely any ADC, no touch sensors, no CAN, bare minimum of USART/I2C/SPI, no I2S, no I3C, no ethernet, no USB PD...

And yeah, it has its PIO modules, but those aren't powerful enough to make up for it. They are fine as an alternative to bitbanging Neopixels, but you can't rely on some hobbyist's vibe-coded weekend PIO project which takes up all the PIO slices and 30% of one core to do application-critical communications.

I would take an RP2000 in a heartbeat for most of my hobbyist products, but for anything professional an STM32 is orders of magnitudes better, and even a CH32v303 looks like a more attractive option at first glance.

Re: A third world engineer responds to “RISC-V: They should have known better”

#260

Post by Kudos »

jacquesm wrote: post #32
HawtAds wrote: post #4

I love the article, it's a breath of fresh air compared to the usual bay area centric takes. However there's just one issue: > The students I want to teach are in the same position, and so are the ones in Nigeria and Bangladesh It does not take $60 to ship small sub $1 chips from Asia to Nigeria/Bangladesh. These two countries are all on global trade routes (both supply and demand) and the expensive last mile deliver…

So, you are calling the author a liar?

No, I think he's saying the costs don't need to be so high and certain parties are just taking advantage.
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