Earlier quoted context omitted.
Didn't stop Intel or TSMC from building in Phoenix...where there is literally no water and they are having one of the worst droughts ever.
They'll just get a government bailout so it's no real problem. We are big on corporate socialism
TSMC eyes Germany as possible location for first Europe chip plant
321–330 of 450 posts
Re: TSMC eyes Germany as possible location for first Europe chip plant
#322Make it Munich, make it Munich, make it Munich
Please no, my rent is already high enough as it is and more specialized and skilled technical workers in the area won't drive them down.
Re: TSMC eyes Germany as possible location for first Europe chip plant
#323Earlier quoted context omitted.
Because while TSMC is production, the innovation happens mostly with those companies.
Ya but why does it matter that those organizations are in Europe? The distance does not matter and in any event TSMC is not contemplating building a leading edge plant in Europe
Re: TSMC eyes Germany as possible location for first Europe chip plant
#324Earlier quoted context omitted.
Any thoughts on Chisel?
as much as it pains to say me, but IMO its a wasted effort. we don't need new design languages. VHDL/Verilog "pain points" as RTL are tiny and don't require solving, we pretty much figured out design. Verification, on the other hand, is still an evolving (now stagnating) mess that needs inputs. The biggest offender on that project list is FIRRTL. Cleary outgrew as someone's university work of "hey, lets do IR, but fo…
Parsing Verilog and generating valid Verilog is fairly difficult. If you want to stay with Verilog, the most realistic alternative to firrtl right now is the RTL-IL representation used inside of yosys.
> at worst it does not do the primary function of "being" IR for RTL, because it should've been a graph, not another language with simplified syntax.
Canonicalized LoFirrtl (i.e., the representation the compiler lowers Chisel to) is essentially SSA (single static assignment) which encodes a dataflow DAG. So on a per module level, firrtl does represent the circuit as a graph.
What you might be talking about is the fact that this graph isn't global. Having a global circuit graph could make some analyses easier, but it might require essentially in-lining the whole circuit which is something a lot of designers are opposed to. Even small optimizations like removing unused pins from internal modules are often times opposed.
Chris Lattner and others are currently working on an "industry" version of firrtl as part of the CIRCT hardware compiler framework: https://github.com/llvm/circt As you can see they did not decide to go with a global graph based IR and instead opted to just represent local data-flow graphs as SSA.
Re: TSMC eyes Germany as possible location for first Europe chip plant
#325Earlier quoted context omitted.
It is necessary to grind in a random fashion (OP is talking about the method of grinding, not the order), or you will end up with imperfections. Lots of info about this if you look in to grinding mirrors for telescopes. Also, the order being random wouldn't effect the end result.
When grinding the concave plate why didn't that make then other flat plate convex again?
I'll add that this depends on the materials having similar properties, so when ground together, they are grinding each other. This means whatever residual shape you have in one of them, it won't be transferred completely to the other.
If the materials had very different hardnesses, one of them would dominate over the other when they're ground together.
Re: TSMC eyes Germany as possible location for first Europe chip plant
#326From a security point of view, it's interesting that they don't look to build a fab in the UK. Given that the Europe used to be an arena of devastating conflicts - with things like completely levelled down cities, to murders on an industrial scale, the long term investment like this may be subject to a lot of uncertainty as the EU moves closer towards being an authoritarian regime, this may wake up internal conflicts…
The last European war was over 70 years ago and today it is one of if not the most stable regions in the world. The idea that they are doom spiralling into authoritarianism is a conspiracy theory that is easy to dismiss.
Re: TSMC eyes Germany as possible location for first Europe chip plant
#327TSMC is really the keystone for everything else done that ends up getting talked about on this website. They are constantly at the bleeding edge of computer manufacture and pushing it further still. We should feel some sense of amazement to be alive still in the middle of the computer revolution.
Overall semiconducting industry seems to be way more exciting than boring computer industry
Re: TSMC eyes Germany as possible location for first Europe chip plant
#328Earlier quoted context omitted.
"A decent mostly free health system" Where in Germany is that? You either pay a lot for private insurance (especially when you get old) or you pay a lot for state-backed insurance (which is a lot if you earn above average as most techies do).
Since insurance is capped at around 5k salary you will at most pay 15% of that (750 EUR) for health insurance per month in the universal insurance system. If you make higher salaries then you won't be affected.
For comparison in California, a 35-year-old SF resident earning $250k/yr living alone purchasing insurance through the public marketplace can get a Platinum-level Kaiser Permanente HMO plan for around $650/mo (but over $2000/mo for a family of four).
YMMV but I've found KP's service quality to be extremely high, and that plan comes with $0 annual deductible and very low copays.
Re: TSMC eyes Germany as possible location for first Europe chip plant
#329Re: TSMC eyes Germany as possible location for first Europe chip plant
#330I'm not sure why they didn't consider the UK, plenty of high tech here and the Russians won't find us a walk over if they ever do come.
I think there are some obvious trade barriers that the British imposed upon themselves.