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Reviewing Bad Schematics as EE Interview Tactic

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Re: Reviewing Bad Schematics as EE Interview Tactic

#31

Post by dws »

fest wrote: post #23

Things that come to mind for bad schematic review: * Linear voltage regulator with high input voltage powering an obviously very power hungry load. * No ESD protection/current limiting for sensitive pins exposed to outside world. * Tantalum capacitors with very narrow voltage rating margin Another tactic I like (something similar is mentioned in sibling comment): a small design problem representative of real life tas…

The same approach works. Under-specify a problem, then see what questions candidate asks, and at what level they jump in. When Windows used to ship with Minesweeper, I'd ask candidates how they'd approach implementing Minesweeper for a touchscreen on an embedded device. Good candidates would get clarity on hardware and constraints first.

Re: Reviewing Bad Schematics as EE Interview Tactic

#32

Post by Treblemaker »

I get that this is intended to be a general exercise in spotting schematic errors. But as someone who brought-up and debugged numerous complex power supply boards for mobile electronics, it seems to me the most important and useful bit of information is missing from this exercise: show me where the smoke came out!

Re: Reviewing Bad Schematics as EE Interview Tactic

#33

Post by TrackerFF »

SilasX wrote: post #14
rightbyte wrote: post #3

Earlier quoted context omitted.

It seems strange that the author has not met a single one that understands that concept since it is quite basic. I am guessing he just is bad at interviewing and asks trick questions till he meet someone who know the interviewing game inside out. Examples he gives: "Current limiting resistors missing (BJTs, diodes, etc.) Shorting a potentiometer node to a rail Voltage regulators missing capacitors at input/output Mis…

>It seems strange that the author has not met a single one that understands that concept since it is quite basic. That's exactly what everyone says when candidates fail FizzBuzz. The best explanation I know is that good candidates get hired quickly, so at any given moment, the candidate pool is dominated by people who keep failing questions like this.

There are some variables at play.

- Stress-levels of the candidate - Tone / demeanor of interviewer - Communication prior to interview

I mean, sure, if you fail fizzbuzz interviews 10 times in a row, there seems to be some pattern going. But you could might as well fail it the first time, and get blackballed as incompetent.

Re: Reviewing Bad Schematics as EE Interview Tactic

#34

Post by TrackerFF »

Sanzig wrote: post #12
userbinator wrote: post #2

My example of this: I have yet to meet a junior EE candidate who understands the need for decoupling capacitors in digital circuits That says a lot about the state of education. I'm not even officially an EE, and only did some embedded hardware stuff and some electronics as a hobby, yet I know what that's about.

I'm an EE. My first job out of university had a pretty good whiteboard interview (I know - we're not supposed to say good things about whiteboard interviews on HN). I thought the process was pretty straightforward. The first exchange went something like this: Interviewer: "Can you draw me the schematic symbol for an LED?" Me: Draws LED schematic symbol. Interviewer: "What would you say the forward voltage is on that…

When I got my BSEE, there were unfortunately only two types of professors:

1. Extremely theoretical, minimal practical elements (labs, demos, etc.). These would have classes in Electromagnetism, Signal and systems, ICs, RF, Optics, etc.

2. Very practical, but only skin deep on theory. Power systems, electrical circuits, electrical machines, etc.

The very few classes where we had a nice 50/50 ratio of theory / work were perfect, but I always felt like missing out on the other classes. Unfortunately the coursework was quite heavy, so you didn't get much time to do self-study either. Labs always crammed, always some projects / HW / home exams / labs that needed be handed in.

Re: Reviewing Bad Schematics as EE Interview Tactic

#35

Post by rasz »

quasse wrote: post #4
userbinator wrote: post #2

My example of this: I have yet to meet a junior EE candidate who understands the need for decoupling capacitors in digital circuits That says a lot about the state of education. I'm not even officially an EE, and only did some embedded hardware stuff and some electronics as a hobby, yet I know what that's about.

Seems like it says more about the writer's hiring pool. I can't think of one junior EE I've interacted with who couldn't have told you what decoupling caps were for. Sizing them correctly (instead of just sprinkling the 0.1uF magic fairy dust on your board) might be another matter but I've yet to see someone fail to grasp the purpose.

I know few who never touched soldering iron.

Re: Reviewing Bad Schematics as EE Interview Tactic

#36

Post by xvector »

SilasX wrote: post #24
rightbyte wrote: post #18

Earlier quoted context omitted.

He is saying that all juniors fail EE-FizzBuzz, which makes me question his interviewing skills.

And a lot of interviewers report that all juniors fail FizzBuzz.

I just refuse to believe this. It can’t be.

Re: Reviewing Bad Schematics as EE Interview Tactic

#37

Post by mlyle »

> Then, you give them a fake schematic of the circuit board, and ask them to troubleshoot the problem.

> Here’s the test: the fake board schematic should be absolutely riddled with errors. All sorts of errors - errors that you’ve seen before, errors that you’ve heard about before, errors that have thrown your product development efforts for a loop. These errors should run the gamut of severity

I think you need to communicate to the candidate that this is a board with a lot wrong. If you hand me something that looks like a real board made by the organization, and it's of exceptionally poor quality-- panic will ensue. Is there a single issue I'm supposed to point out? Is the interviewer not aware of how bad this is? Do I even want to work at a place producing shoddy work like this?

Re: Reviewing Bad Schematics as EE Interview Tactic

#38

Post by mkeeter »

spatular wrote: post #20
rightbyte wrote: post #15

Earlier quoted context omitted.

I hate to maybe be proving his point by showing that I'm not into the EE field and thinking of a board mounted DCDC-converter as a voltage regulator (which it is but not what you usually call it in english?) I would still argue that logic IC have alot of internal pull ups. Or that eg. "Reset sequence of digital component is wrong" is a bad whiteboard question.

I believe that without qualification "linear regulator" could be just anything that regulate voltage. Usually you can easily tell from schematics around it if it's some switching IC, an LDO or a module. And if you have layout or 3d render of the board it'd be almost certain. Otherwise the person may just ask: "where are caps, or is this thing a module or what?"

In my experience, "linear regulator" refers specifically to voltage regulators which drop from a high voltage to a lower voltage by burning all of the power in between (e.g. the venerable 7805).

They're useful if the voltage drop isn't too large and/or if you need a particularly stable output voltage; contrast them with switching regulators, which are more efficient but have some amount of output ripple.

One design that I worked on used a switching regulator to generate 5V, then linear regulators to generate something like 3.7V and 2.9V for various sensitive analog circuits.

Re: Reviewing Bad Schematics as EE Interview Tactic

#39

Post by mlyle »

userbinator wrote: post #17
Sanzig wrote: post #12

Earlier quoted context omitted.

I'm an EE. My first job out of university had a pretty good whiteboard interview (I know - we're not supposed to say good things about whiteboard interviews on HN). I thought the process was pretty straightforward. The first exchange went something like this: Interviewer: "Can you draw me the schematic symbol for an LED?" Me: Draws LED schematic symbol. Interviewer: "What would you say the forward voltage is on that…

The closest standard value for that resistor would be a 3k3, if I'm not mistaken... In the software industry we have a similar problem; alot of people can follow instructions on how to glue together lots of libraries and frameworks, but have no idea how to go beyond that --- or understanding of how computers work in general --- much less debug it when something goes wrong. There's a classic article about this: https:…

Yah, but IMO 1mA is on the "low end" of lit, so you want to round down the resistor value to get a little more current. Pick 2k7 instead.

Most small LEDs will tolerate per datasheet 20mA; 4mA is "well-lit". A little less than 1mA is going to be pretty anemic looking on lots of LEDs.

So I'd be more inclined to put down 470 to 1k5.

Re: Reviewing Bad Schematics as EE Interview Tactic

#40

Post by analog31 »

emmelaich wrote: post #27

> ...should be absolutely riddled with errors. Same applies to code in an interview; it should have syntax, efficiency, correctness errors and more.

You should use your own production code. This will kill two birds with one stone: Does the candidate know how to read code? Is your production code readable?
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