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Can someone enlighten me with some information about application requiring the full 16x PCIe gen4 bandwidth per slot (or 32x gen3 for that matter)? I can imagine some HPC GPU solutions but other than that what requires the thoughput? There is obviously a market for this as both giants are building platforms.
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Virtualization. Remember that these EPYC systems will have up to 64 cores per chip. 128 cores / 256 threads per 2P platform, with 128x to 160x PCIe 4.0 lanes depending on the motherboard. Lets say you split up your system into 32 VMs (4-cores / 8-threads per VM). That's only 4x to 6x PCIe 4.0 lanes per VM. Doesn't seem very spacious anymore, does it? That's barely enough room for a NVMe drive per VM + a small, shared…
This, exactly. These chips are targeted for the heavy virtualization platforms (see: "The Cloud"). It means you can fit more customers in the same space and power envelope before you start running into noisy neighbor issues.
They're very nice for big fast storage: https://www.dell.com/en-us/work/shop/povw/poweredge-r7415
> Front Drive Bays: Up to 24 x 2.5” […] NVMe
That's 96 PCIe lanes right there., and drives are bandwidth-limited by 3x4.
Especially if you want to plug that into a fast network, you need 3x16 per 100Gb port, or half a 4x16.
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NVMeOF (NVMe Over Fabrics) comes to mind, having multiple NVMe drives (mostly PCIe x4) + networking (100GbE uses x16 PCIe) consumes a lot of PCIe lanes. Also note that current two-socket AMD Epyc servers use 64 lanes from each CPU for inter-CPU communication, so the entire server has only 128 lanes (out of 256) left for peripherals.
Current Epyc servers have PCIe 3.0 connections. They could use half as many PCIe 4.0 connections and get the same bandwidth.
>why the AMD EPYC “Rome” generation will likely see 160x PCIe Gen4 lanes plus likely additional lane(s) for a necessary function. Emphasis mine. This seems to be pure speculation, not 'news'.
Can someone enlighten me with some information about application requiring the full 16x PCIe gen4 bandwidth per slot (or 32x gen3 for that matter)? I can imagine some HPC GPU solutions but other than that what requires the thoughput? There is obviously a market for this as both giants are building platforms.
Not an expert, but at least on the gaming side of GPUs my understanding is that you usually aren't using the bandwidth much. For rendering your average frame, all the data you need is already in VRAM. But if there's new model or textures that aren't yet on the GPU, you want to move them over quickly because the next frame needs to go out ASAP. For a game running at 60hz you've got 16ms to avoid a frame delay. At 144h…
The average impact is low, but frametime consistency is generally deteriorated much more strongly than the small reduction (0-5 %) of average FPS suggests. That is probably mostly due to blocking uploads, where having a multitude more bandwidth reduces the blocking time. The average reduction is probably more caused by the general area of latency, since modern renderers tend to do a bunch of queries and while they obviously try to avoid it they'll have some amount of blocking commands in each frame frame.
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Current Epyc servers have PCIe 3.0 connections. They could use half as many PCIe 4.0 connections and get the same bandwidth.
Yeah but realistically NVMe will remain on 4x and you'll get faster drives. It allows for double the number of ports in NICs though, which is really useful for 10+Gb (and especially 100)
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AMD's been adding more PCIe lanes across their hardware lineup than Intel has to be sure, but EPYC is server-class stuff with 64 cores to a chip. The Ryzen 2 2700X only has 20 lanes for 8 cores.
I don't watch this as closely as a lot of people, but my impression is that Intel has been rationing lanes as one way to segment their market, and AMD noticed they can easily mess with that strategy. I spent significantly more for the CPU on a personal build a few years ago because I needed 40 lanes instead of 24. I'm all for AMD messing with it.
That, and the eye-popping multithreaded performance for encoding.
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A good target is storage, ie a lot of NVMe drives.
Yeah, that's why most PCIe M2 top out at around 3500 MB/s, I doubt it will take long to saturate 7 GB/s (or double that in RAID0). Either way, it's a heck of a lot of bandwidth!
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AMD's been adding more PCIe lanes across their hardware lineup than Intel has to be sure, but EPYC is server-class stuff with 64 cores to a chip. The Ryzen 2 2700X only has 20 lanes for 8 cores.
I don't watch this as closely as a lot of people, but my impression is that Intel has been rationing lanes as one way to segment their market, and AMD noticed they can easily mess with that strategy. I spent significantly more for the CPU on a personal build a few years ago because I needed 40 lanes instead of 24. I'm all for AMD messing with it.
And Intel got away with it because they had no competition. Monopolies are always very, very bad for consumers.
Meanwhile i9 9900k still has only 16 3.0 lanes ...
They had the monopoly for a long time, so they turned into a money-making machine first and a chip company a distant 4th or 3rd.