Meanwhile i9 9900k still has only 16 3.0 lanes ...
AMD's been adding more PCIe lanes across their hardware lineup than Intel has to be sure, but EPYC is server-class stuff with 64 cores to a chip. The Ryzen 2 2700X only has 20 lanes for 8 cores.
AMD EPYC Rome 2P Will Have 128-160 PCIe Gen4 Lanes and a Bonus
21–30 of 66 posts
Re: AMD EPYC Rome 2P Will Have 128-160 PCIe Gen4 Lanes and a Bonus
#22Earlier quoted context omitted.
Off the top of my head this would be great for massive enterprise VDI installations and game streaming services (which is just VDI by another name), ML, AI applications, and NVMe storage. Personally, this will be good for me because everything I do is bandwidth-starved. I'm not a radar scientist but I am a systems engineer supporting radar scientists working on air- and space-based Synthetic Aperture Radar (SAR) syst…
Hmmm, how many radar pulses need to hit a target to generate video? Sounds potentially irradating... ;) eg: WARNING Don't attempt to image living creatures WARNING
RADAR typically uses microwaves, non-ionizing. Over this area it's bound to be a terribly, terribly small amount of exposure.
Re: AMD EPYC Rome 2P Will Have 128-160 PCIe Gen4 Lanes and a Bonus
#23>why the AMD EPYC “Rome” generation will likely see 160x PCIe Gen4 lanes plus likely additional lane(s) for a necessary function. Emphasis mine. This seems to be pure speculation, not 'news'.
Likely is there because it requires that AMD's partners release servers in this configuration, and those servers are unreleased. In theory, something during validation could prevent it or partners could decide not to release this configuration (which are unlikely but still possible.)
Re: AMD EPYC Rome 2P Will Have 128-160 PCIe Gen4 Lanes and a Bonus
#24Can someone enlighten me with some information about application requiring the full 16x PCIe gen4 bandwidth per slot (or 32x gen3 for that matter)? I can imagine some HPC GPU solutions but other than that what requires the thoughput? There is obviously a market for this as both giants are building platforms.
HPC as you mentioned, but also 200Gbps NICs need it, and those are available today.
Re: AMD EPYC Rome 2P Will Have 128-160 PCIe Gen4 Lanes and a Bonus
#25Can someone enlighten me with some information about application requiring the full 16x PCIe gen4 bandwidth per slot (or 32x gen3 for that matter)? I can imagine some HPC GPU solutions but other than that what requires the thoughput? There is obviously a market for this as both giants are building platforms.
Here is the easy example:
A dual 100GbE NIC requires a PCIe Gen4 x16 slot to run both ports at full speed. Mellanox ConnectX-6 200GbE cards require either 2x Gen4 or 1x Gen5 slot for full dual port bandwidth. Most of the larger NVMEoF nodes we are seeing are using more than one 100GbE NIC.
Enterprise SSDs will rapidly fill Gen4 x4 lanes later this year as we start to see them launch alongside more mainstream platforms. Four of those will fill a x16 slot.
GPUs and PCIe switches are also great examples of uses.
You are right that for the high-volume server segment, 160 PCIe lanes are overkill, as is even 128 today frankly. For some context, there is a huge portion of servers sold with less than 1 DIMM per RAM channel installed.
Re: AMD EPYC Rome 2P Will Have 128-160 PCIe Gen4 Lanes and a Bonus
#26>why the AMD EPYC “Rome” generation will likely see 160x PCIe Gen4 lanes plus likely additional lane(s) for a necessary function. Emphasis mine. This seems to be pure speculation, not 'news'.
They claim to have confirmed this with AMD partners. So it's more than just speculation.
Re: AMD EPYC Rome 2P Will Have 128-160 PCIe Gen4 Lanes and a Bonus
#27Can someone enlighten me with some information about application requiring the full 16x PCIe gen4 bandwidth per slot (or 32x gen3 for that matter)? I can imagine some HPC GPU solutions but other than that what requires the thoughput? There is obviously a market for this as both giants are building platforms.
NVMeOF (NVMe Over Fabrics) comes to mind, having multiple NVMe drives (mostly PCIe x4) + networking (100GbE uses x16 PCIe) consumes a lot of PCIe lanes. Also note that current two-socket AMD Epyc servers use 64 lanes from each CPU for inter-CPU communication, so the entire server has only 128 lanes (out of 256) left for peripherals.
Current Epyc servers have PCIe 3.0 connections. They could use half as many PCIe 4.0 connections and get the same bandwidth.
Re: AMD EPYC Rome 2P Will Have 128-160 PCIe Gen4 Lanes and a Bonus
#28Can someone enlighten me with some information about application requiring the full 16x PCIe gen4 bandwidth per slot (or 32x gen3 for that matter)? I can imagine some HPC GPU solutions but other than that what requires the thoughput? There is obviously a market for this as both giants are building platforms.
Virtualization. Remember that these EPYC systems will have up to 64 cores per chip. 128 cores / 256 threads per 2P platform, with 128x to 160x PCIe 4.0 lanes depending on the motherboard. Lets say you split up your system into 32 VMs (4-cores / 8-threads per VM). That's only 4x to 6x PCIe 4.0 lanes per VM. Doesn't seem very spacious anymore, does it? That's barely enough room for a NVMe drive per VM + a small, shared…
This, exactly. These chips are targeted for the heavy virtualization platforms (see: "The Cloud"). It means you can fit more customers in the same space and power envelope before you start running into noisy neighbor issues.
Re: AMD EPYC Rome 2P Will Have 128-160 PCIe Gen4 Lanes and a Bonus
#29Meanwhile i9 9900k still has only 16 3.0 lanes ...
Intel just dropped a bunch of details about the actual competitor to EPYC, Cascade Lake AP. These server chips will have 48 PCI-E 3.0 lanes, still not anywhere near the EPYC's claimed amount, but definitely better than what they are selling to the niche high-end gamers.
Re: AMD EPYC Rome 2P Will Have 128-160 PCIe Gen4 Lanes and a Bonus
#30Meanwhile i9 9900k still has only 16 3.0 lanes ...
AMD's been adding more PCIe lanes across their hardware lineup than Intel has to be sure, but EPYC is server-class stuff with 64 cores to a chip. The Ryzen 2 2700X only has 20 lanes for 8 cores.
I don't watch this as closely as a lot of people, but my impression is that Intel has been rationing lanes as one way to segment their market, and AMD noticed they can easily mess with that strategy.
I spent significantly more for the CPU on a personal build a few years ago because I needed 40 lanes instead of 24. I'm all for AMD messing with it.