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AMD Tackles Coming “Chiplet” Revolution With New Chip Network Scheme

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Re: AMD Tackles Coming “Chiplet” Revolution With New Chip Network Scheme

#31

Post by chris_st »

corysama wrote: post #28
bokchoi wrote: post #26

It reminds me of the GreenArrays chip created by Chuck Moore. There was some hubbub here on HN a few years ago about it -- what ever happened to it? http://www.greenarraychips.com/

It certainly does seem like chip design is marching grudgingly from Core i7 to Cell BE and eventually to Connection Machine. Physics doesn’t really care about ease of programming. https://en.m.wikipedia.org/wiki/Cell_(microprocessor) https://en.m.wikipedia.org/wiki/Connection_Machine

For the record, C* on the Connection Machine was a great language to program with.

Re: AMD Tackles Coming “Chiplet” Revolution With New Chip Network Scheme

#32

Post by greglindahl »

sixdimensional wrote: post #30

I wonder if FPGAs could be a node too. That would allow us to mix programmable, highly parallel analog modeled acceleration onto the same high speed / direct connect bus as all the other fixed, traditional computing components. I really like the approach AMD is suggesting here, treating it like nodes on a network.

You've been able to buy FPGAs tightly coupled with AMD CPUs since 2006 or so. The tech back then was to either plug them into an HTX Hypertransport slot, or in a cpu socket. Very few customers actually wanted to buy these things and I think all of the makers lost money.

Re: AMD Tackles Coming “Chiplet” Revolution With New Chip Network Scheme

#33

Post by greglindahl »

Quequau wrote: post #18

I think would be interesting to see someone like Mellanox make a chiplet with their tech which could be fully integrated into an AMD SoC or APU or whatever they're calling them now.

Check out Intel Omni-Path, it's a separate chip on-package for Intel's high end cpus. 100 gigabit network.

Re: AMD Tackles Coming “Chiplet” Revolution With New Chip Network Scheme

#34

Post by petra »

dragontamer wrote: post #21

The main issue AMD seems to be solving here is the yields at 7nm and lower processes. Smaller chips means that you get more yield in the presence of errors. Intel builds relatively large 600mm^2 chips (like the XCC aka the 28-core Xeon), but AMD thinks the future is to build networks of ~200mm^2 chips, like what they've done with Zen / Threadripper / EPYC. The advantage for AMD is that they've built a single design:…

What about business implications of chiplets ?

Does it mean it would be easier for companies to cooperate, so in one chip you'll get best parts from the leaders ? or does IP already solves that ?

Re: AMD Tackles Coming “Chiplet” Revolution With New Chip Network Scheme

#35

Post by Quequau »

greglindahl wrote: post #33
Quequau wrote: post #18

I think would be interesting to see someone like Mellanox make a chiplet with their tech which could be fully integrated into an AMD SoC or APU or whatever they're calling them now.

Check out Intel Omni-Path, it's a separate chip on-package for Intel's high end cpus. 100 gigabit network.

I can't afford Intel's high-end stuff. That's why I'm looking at AMD.

Re: AMD Tackles Coming “Chiplet” Revolution With New Chip Network Scheme

#36

Post by fyi1183 »

petra wrote: post #34
dragontamer wrote: post #21

The main issue AMD seems to be solving here is the yields at 7nm and lower processes. Smaller chips means that you get more yield in the presence of errors. Intel builds relatively large 600mm^2 chips (like the XCC aka the 28-core Xeon), but AMD thinks the future is to build networks of ~200mm^2 chips, like what they've done with Zen / Threadripper / EPYC. The advantage for AMD is that they've built a single design:…

What about business implications of chiplets ? Does it mean it would be easier for companies to cooperate, so in one chip you'll get best parts from the leaders ? or does IP already solves that ?

There's already been an example of this with the AMD + Intel combination sold by Intel in the Hades Canyon NUC. It's an Intel CPU and an AMD GPU in a single package on some sort of interposer.

The more common approach is via SOCs though.

Re: AMD Tackles Coming “Chiplet” Revolution With New Chip Network Scheme

#37

Post by jostmey »

dragontamer wrote: post #21

The main issue AMD seems to be solving here is the yields at 7nm and lower processes. Smaller chips means that you get more yield in the presence of errors. Intel builds relatively large 600mm^2 chips (like the XCC aka the 28-core Xeon), but AMD thinks the future is to build networks of ~200mm^2 chips, like what they've done with Zen / Threadripper / EPYC. The advantage for AMD is that they've built a single design:…

Writing code to run in parallel across a large number of small "chips" is probably the future of programming. In this sense, new programming languages like Julia might prove useful?

Re: AMD Tackles Coming “Chiplet” Revolution With New Chip Network Scheme

#38

Post by dragontamer »

petra wrote: post #34
dragontamer wrote: post #21

The main issue AMD seems to be solving here is the yields at 7nm and lower processes. Smaller chips means that you get more yield in the presence of errors. Intel builds relatively large 600mm^2 chips (like the XCC aka the 28-core Xeon), but AMD thinks the future is to build networks of ~200mm^2 chips, like what they've done with Zen / Threadripper / EPYC. The advantage for AMD is that they've built a single design:…

What about business implications of chiplets ? Does it mean it would be easier for companies to cooperate, so in one chip you'll get best parts from the leaders ? or does IP already solves that ?

Well, consider that MCMs have existed for decades: https://en.wikipedia.org/wiki/Multi-chip_module

So in many regards, these "chiplets" aren't new, at least conceptually. What needs to happen is for the protocols to be redefined and respec'd for today's technology.

In particular: the silicon interposer allows for many more connections than previous technologies, as well as much lower power consumption. So protocols need to be designed with those power-requirements and huge "pin counts" so to speak.

Consider HBM2: its a 1024-bit bus. But there's four of them per Vega64, so that's 4096-wires on the interposer connecting the GPU to the RAM.

This is a level of integration never before seen, even in the MCM world. The future is with larger pin counts at far lower energy costs than before.

So its not so much that these problems are purely research. They're closer to engineering. There already exist protocols for cache coherency or fast communications at these levels, they just need to be tweaked for the new scale of things.

Re: AMD Tackles Coming “Chiplet” Revolution With New Chip Network Scheme

#39

Post by rb808 »

dragontamer wrote: post #21

The main issue AMD seems to be solving here is the yields at 7nm and lower processes. Smaller chips means that you get more yield in the presence of errors. Intel builds relatively large 600mm^2 chips (like the XCC aka the 28-core Xeon), but AMD thinks the future is to build networks of ~200mm^2 chips, like what they've done with Zen / Threadripper / EPYC. The advantage for AMD is that they've built a single design:…

Wow I didn't realize AMD were so close with 7nm. looks like I need a new PC next year. https://www.overclock3d.net/news/cpu_mainboard/amd_s_7nm_epy...

Re: AMD Tackles Coming “Chiplet” Revolution With New Chip Network Scheme

#40

Post by gigatexal »

garmaine wrote: post #15
tzahola wrote: post #3

Earlier quoted context omitted.

>As long as there’s a decent SDK that abstracts the hard stuff away I'd be very skeptical of that. See: Cell Broadband Engine.

Pointing to one example of someone failing to do something in the past is not strong evidence it won’t happen this time. If anything there was lessons learned from that failure.

That’s very true, too.
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