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MIPS Becomes RISC-V

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Re: MIPS Becomes RISC-V

#221

Earlier quoted context omitted.

I don't know if MIPS is the same, but I worked on an other architecture where NOP is 0x0, and it had an interesting effect. If you called an uninitialized function pointer, and it happened to point into zero:ed out memory, the CPU would execute NOPs for a good while until it hit something else. If that something else was code, it would start executing some function from the start, but with garbage arguments. It would…

Seems like a better design choice would be to have instruction 0x0 throw some kind of page fault violation or other exception the OS can catch then.

It is and on RISC-V 0 (16-bit bits and 32-bit) are an illegal instruction. Jumping to zeroed page is obviously a bug so this is the correct behavior.

Re: MIPS Becomes RISC-V

#222

Earlier quoted context omitted.

> You can buy them on Amazon. > Currently unavailable. We don't know when or if this item will be back in stock. Clearly not!

This board is BL602 based. Available and has a growing community. https://pine64.com/product/pinecone-bl602-evaluation-board/

I have a few of them blinking next to me. They are fine albeit documentation is severely lacking at the moment, but once you realize how cheap they are compared to the alternatives, new possibilities open up.

Interestingly it's based on a 3 stage core from SiFive, not the RocketChip.

Re: MIPS Becomes RISC-V

#223
post #111
post #88

Earlier quoted context omitted.

Check your router's CPU. I own 4 routers and all of them use MIPS. RISC-V is more like Graphene, it's yet to leave the lab.

Ho, ho. Graphene has left the lab, but it's only got as far as the hype mill, not the factory. https://www.manchester.ac.uk/discover/news/the-university-un... was a notable success though; and allegedly graphene-powered trainers there on a different date. In contrast, with RISC-V you can put your hand in your pocket for early models, can't you?

2021 to me really marked at turning point for RISC-V embedded cores. $4 (+ S/H) for a BL602-based pinecone (or any of the many other BL602 boards). Pretty nice.

Re: MIPS Becomes RISC-V

#224
post #74

Everyone's right to celebrate the success of RISC-V, but part of me thinks it's a shame that there's relatively little architectural diversity ( edit I should have said ISA diversity ) in modern CPUs. MIPS, Alpha, and Super-H, have all but faded away. Power/PowerPC is still out there somewhere though. Apparently they're still working on SPARC, too. [0] At least we'll always have the PS2. ...until the last one breaks,…

I wish the barriers to using new architectures were lower. For instance, suppose binaries were typically distributed in a platform-agnostic format, like LLVM intermediate representation or something equivalent. When you run your program the first time, it's compiled to native code for your architecture and cached for later use. I realize I've sort of just re-invented Javascript. But what if we just did away with nati…

1989 is calling with a blast from the past:

https://en.wikipedia.org/wiki/Architecture_Neutral_Distribut...

It didn't last.

Re: MIPS Becomes RISC-V

#225

Everyone's right to celebrate the success of RISC-V, but part of me thinks it's a shame that there's relatively little architectural diversity ( edit I should have said ISA diversity ) in modern CPUs. MIPS, Alpha, and Super-H, have all but faded away. Power/PowerPC is still out there somewhere though. Apparently they're still working on SPARC, too. [0] At least we'll always have the PS2. ...until the last one breaks,…

There isn't much diversity in software, why hardware? Maybe standardization is a strength.

There's a lot of diversity in software. Windows is quite different from GNU/Linux, for instance. There's quite a lot of diversity in the major programming languages.

If you want something really different, whether in operating systems or programming languages, you have it. KolibriOS and Haskell, say.

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