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IBM debuts sub-1 nanometer chip technology

newsroom.ibm.com

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Re: IBM debuts sub-1 nanometer chip technology

#201

Post by sbergot »

measurablefunc wrote: post #101
gruez wrote: post #91

Earlier quoted context omitted.

Not all densities is mass per volume. eg. population density.

It's a physical quantity per some unit of spatial measurement so the units still don't match up b/c in one case the transistors are stacked per volume & in the other case per area. > Historically, "node" sizes (like 28nm or 7nm) directly correlated to the physical length of a transistor's gate. Today, names like 3nm or 2nm reflect a marketing generation. The actual transistors are significantly larger than these nano…

The comparison is good. Humans are also stacked in volumes and we still measure population density over a surface because the third dimension is less significant in this context.

Re: IBM debuts sub-1 nanometer chip technology

#202

Post by jayd16 »

u1hcw9nx wrote: post #139
jayd16 wrote: post #111

Earlier quoted context omitted.

Why not use something absolute, like nand-gates per volume?

Transistor density in units of MTr/mm. (Million Transistors per square mm) is also used. The formula is MTr/mm = 0.6×(NAND2 Tr Count)/(NAND2 Cell Area) + 0.4×(Scan Flip Flop Tr Count)/(Scan Flip Flop Cell Area)

Why do you think it's not commonly used?

Re: IBM debuts sub-1 nanometer chip technology

#203

Post by Loic »

Looking at this picture: https://filecache.mediaroom.com/mr5mr_ibmnewsroom/201436/IBM...

I am just astonished at the quality of the structure. Not only that, but the quality of the "cut" to then be able to take this picture. I was closely involved in EM imaging more than 30 years ago, this is just wonderful to see such pictures now.

Re: IBM debuts sub-1 nanometer chip technology

#204

Post by measurablefunc »

sbergot wrote: post #201
measurablefunc wrote: post #101

Earlier quoted context omitted.

It's a physical quantity per some unit of spatial measurement so the units still don't match up b/c in one case the transistors are stacked per volume & in the other case per area. > Historically, "node" sizes (like 28nm or 7nm) directly correlated to the physical length of a transistor's gate. Today, names like 3nm or 2nm reflect a marketing generation. The actual transistors are significantly larger than these nano…

The comparison is good. Humans are also stacked in volumes and we still measure population density over a surface because the third dimension is less significant in this context.

I got the answer from the AI I was looking for & it makes sense. You can try to map the volumetric density to areal density but the mapping is not canonical so it doesn't say anything about the physical reality of actual transistor density since the reality is that it is a volumetric measure that gets fudged for marketing purposes. 3D volume for chips is going to keep increasing so they will eventually transition to measuring density over volume instead of area.

Re: IBM debuts sub-1 nanometer chip technology

#205

Post by wolvesechoes »

Oras wrote: post #187
pjmlp wrote: post #171

Earlier quoted context omitted.

People love to hate on IBM, ask why it is relevant today, while several of their beloved FOSS projects are in some way, form or fashion, made possible with IBM's money.

which beloved FOSS were funded by IBM?

Seems they own Red Hat, which is some no-name company that has nothing to do with Linux.

Re: IBM debuts sub-1 nanometer chip technology

#206

Post by bobby_zhu »

Legend2440 wrote: post #47
buran77 wrote: post #10

> logic technology can extend for the first time below the 1 nm node, advancing the era of angstrom-level scaling, where dimensions approach the size of individual atoms. While transistor nodes now refer to a generation of manufacturing technology versus an exact physical dimension, IBM’s 0.7 nm technology—also referred to as 7 angstroms—demonstrates how continued scaling remains possible. Continuing the well establi…

It's been decades since published node sizes had any connection to actual feature size. Sadly this is just how it works in the semiconductor industry now.

We've already been through years of "7nm isn't actually 7nm" across different fabs - completely different measurement conventions, none corresponding to real feature sizes. Now sub-1nm? If it is real then at that scale we're probably in the several atom width territory.

Re: IBM debuts sub-1 nanometer chip technology

#208

Post by yencabulator »

Loic wrote: post #203

Looking at this picture: https://filecache.mediaroom.com/mr5mr_ibmnewsroom/201436/IBM... I am just astonished at the quality of the structure. Not only that, but the quality of the "cut" to then be able to take this picture. I was closely involved in EM imaging more than 30 years ago, this is just wonderful to see such pictures now.

I understand the general area of "small imaging and manipulation" is something IBM has been working on for a very long time. This is STM from 1989:

https://sciencephotogallery.com/featured/ibm-atom-manipulati...

Re: IBM debuts sub-1 nanometer chip technology

#209

Post by MengerSponge »

meindnoch wrote: post #191
adrian_b wrote: post #59

Earlier quoted context omitted.

As it can be seen from the photos, horizontally the features are much bigger than 5 nm. For silicon, the gate length of a FET has a lower limit somewhere between 10 nm and 15 nm. The current CMOS manufacturing processes have not reached the limit yet. For making smaller transistors, a transition to other semiconductor materials will be necessary. The vertical thicknesses of various layers may be of only a few nanomet…

>The vertical thicknesses of various layers may be of only a few nanometers or even of a fraction of a nanometer We should flip the transistors sideways then!

Shades of

"You can't go to the sun! You'll burn alive!"

"Duh! That's why we're going at night!"

Re: IBM debuts sub-1 nanometer chip technology

#210

Post by ternaryoperator »

lizknope wrote: post #131
ternaryoperator wrote: post #114

Earlier quoted context omitted.

Their line of POWER chips are used in their mainframes

No, their mainframes use the zArch which goes back to the System/360 from 1964. https://en.wikipedia.org/wiki/Z/Architecture IBM sells huge servers with POWER architecture CPUs but they are not what people are referring to when they talk about IBM mainframes.

Ah, thanks for the correction.
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