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AMD Discloses Initial Zen 2 Details

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Re: AMD Discloses Initial Zen 2 Details

#201

Post by ksec »

gmueckl wrote: post #172
saiya-jin wrote: post #160

Earlier quoted context omitted.

For a gamer, Nvidia's latest card offering is vastly disappointing. Technology that is not there and won't be there for maybe next 6 years (if they stick to 3 year release cycle), offering some shiny surfaces at best, at massively increased price. I really hope AMD will come with some good cheaper competition. Gamers want fast framerates, high polygon count, high textures much more than some currently-useless raytrac…

I don't get the ridiculous pricing of the current generation of nVidia chips, either. But this generation of hardware is at the same time an important step towards getting rendering algorithms that have vastly superior quality while having a much simpler structure. I know that anybody that works on high quality real time renderers and knows what they are doing wants this switch to happen.

Buying an 800mm2 Die along with 12GB GDDR6 Memory for $999 isn't really ridiculous. Try getting Intel or AMD to sell you an 800mm2 CPU Die for $999. As a matter of fact I thought it was reasonably priced in terms of Die Size and Transistors. Now whether those 800mm2 perform up to our expectation is an entirely different matter.

Re: AMD Discloses Initial Zen 2 Details

#202

Post by pcwalton »

pjmlp wrote: post #150
geezerjay wrote: post #149

Earlier quoted context omitted.

> Then they made a bad standard to start with. Nonsense. You'll be hard-pressed to find a platform that doesn't support C or a competent system design or even graphics design engineer who isn't confortable with C. If their goal is to establish standards, they build upon standards.

Developers jumping on CUDA due to lack of C++ and Fortran support on OpenCL proves how good that decision was. Likewise for game consoles, Windows and now Apple graphics APIs. Defining standards does not mean they must provide a lowest denominator single implementation. They can be defined in an IDL kind of way, like e.g. WebIDL, abstractly e.g. Internet RFCs, or define mappings to all major languages in the GPGPU fi…

> They can be defined in an IDL kind of way, like e.g. WebIDL, abstractly e.g. Internet RFCs, or define mappings to all major languages in the GPGPU field, namely C, C++ and Fortran.

That's already done. Mozilla's Obsidian is an object-oriented WebIDL interface to Vulkan: https://github.com/KhronosGroup/WebGLNext-Proposals/tree/mas...

Again, Khronos is just a standards group. It does what its members tell it to. Khronos is far more lightweight of an organization than, say, ISO's C++ committee. Instead of blaming Khronos, you could perhaps encourage them to focus on initiatives like Obsidian.

Re: AMD Discloses Initial Zen 2 Details

#203

Post by rasz »

mda wrote: post #198
rasz wrote: post #196

Earlier quoted context omitted.

IO is 100% analog. Slew rates, crosstalk, reflections, routing, etc. It is literary called Black Magic in EE community. Must read "High Speed Digital Design: A Handbook of Black Magic": https://books.google.pl/books/about/High_speed_Digital_Desig...

I am not sure our definition of analog are same. Are you claiming that gigantic chip shown in the zen 2 picture is an analog chip?

Whole CPU is analog, just hidden away under vendor(cadence/mentor/synopsys/etc) supplied RTL IP building blocks (GDS libraries) abstraction whose specification is highly customized to particular fab house. This lets you design logic part of the circuit without getting into analog hell.

The difference between logic part of CPU and IO is in the amount of work spend on RTL vs direct custom layout of geometric structures on the chip.

Re: AMD Discloses Initial Zen 2 Details

#204

Post by phkahler »

monocasa wrote: post #194
phkahler wrote: post #184

Earlier quoted context omitted.

Instruction set and the number of registers visible to the programmer influence the practical limits to issue width. AMD64 (x86_64) only has 16 general purpose registers, so there are limits to how many instructions could possibly execute at one time. If I recall correctly the ARM ISA has 32 registers, so there is potential for a lot more data sitting there ready to do something on any given cycle. There are limits i…

I've heard from a CPU designer that the CISC nature of x86 lets it punch above it's weight in terms of what you're talking about. There's a lot of instructions that don't reference any architectural registers, but get allocated physical registers (and would have architectural registers allocated when compiled to something RISC). He claimed it was about equivalent to a 32 register RISC for that reason.

x86 has plenty of instructions that use data from memory as one of the operands. I'm sure that offsets the limited number of registers somewhat.

In the end it's all deep in the details. What I'd really like to see is a RISC-V implementation done by a full team at Intel, AMD, or IBM. Even an ARM implementation by those teams would make a great comparison, but that seems even less likely ;-)

Re: AMD Discloses Initial Zen 2 Details

#205

Post by monocasa »

phkahler wrote: post #204
monocasa wrote: post #194

Earlier quoted context omitted.

I've heard from a CPU designer that the CISC nature of x86 lets it punch above it's weight in terms of what you're talking about. There's a lot of instructions that don't reference any architectural registers, but get allocated physical registers (and would have architectural registers allocated when compiled to something RISC). He claimed it was about equivalent to a 32 register RISC for that reason.

x86 has plenty of instructions that use data from memory as one of the operands. I'm sure that offsets the limited number of registers somewhat. In the end it's all deep in the details. What I'd really like to see is a RISC-V implementation done by a full team at Intel, AMD, or IBM. Even an ARM implementation by those teams would make a great comparison, but that seems even less likely ;-)

> x86 has plenty of instructions that use data from memory as one of the operands.

And the fact that you can have a full register width immediates in a single instruction means that you don't have to allocate an architectural register for intermediate immediate construction.

Re: AMD Discloses Initial Zen 2 Details

#206

Post by snuxoll »

blattimwind wrote: post #179
snuxoll wrote: post #59

Earlier quoted context omitted.

Don’t populate all 16 DIMM’s unless you need that much memory? Both my single-socket R320 and dual-socket R520 idle at 70W each with 6 DIMM’s installed. Most people probably don’t need the gobs of memory I have either. A R520 with one socket populated and 2x8 or 16GB dual-ranked RDIMM’s would be more than sufficient.

I actually misspoke. The system above was configured with only 8 DIMMs (8 GB each) at the time. That's the lower limit for this platform before performance is degraded.

Single socket Ivy/Sandy Bridge-EN servers exist and only need three DIMM’s for max performance, that’s what I run FreeNAS on (R320 with a E5-2450L, mind you I have six DIMM’s).

Re: AMD Discloses Initial Zen 2 Details

#207

Post by Kipters »

cantankerous wrote: post #182
Kipters wrote: post #164

Earlier quoted context omitted.

Thanks, as a non native speaker this is very useful for me

FWIW nobody's been a native Latin speaker for a thousand-plus years. You're in the same boat as everybody else! ;-)

True, but the problem is that my language (Italian) only uses "es." for "e.g." and doesn't have an equivalent acronym for "i.e." (we usually use other complete words that roughly translate to "therefore"), so it's easy for me to mix them up since I can't easily map them.
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