21–30 of 45 posts
For those interested in other FPGA boards, Digilent makes a whole series of affordable ones. https://www.digilentinc.com/Products/Catalog.cfm?NavPath=2,4...
https://embeddedmicro.com/tutorials/mojo/
Too bad its dev environment doesn't support OS X though.
Please do yourself a favor and use Verilog instead. I understand that VHDL forces you to write cleaner code, but it's also frustrating for no good reason. Also, start looking into pipelining ASAP. Implement one micro-arch, benchmark it, then try to do better. It's a great way to learn.
Yikes, I find Verilog to be much too C like while VHDL is almost Python like. I enjoy the strictness. VHDL 2008 (should be supported by tools now) fixes a lot of VHDL's warts. Also, I love the two process design methodology that you can use with VHDL. It lets you single-step through your VHDL code in the simulator as if it were plain procedural code! http://www.gaisler.com/doc/vhdl2proc.pdf
>bonus points goes to the people who realise there is an odd thing about the form of the baz (branch if Ra is zero) instruction. Is this because the second argument is another register (presumably containing an address to branch to) instead of a label?
Please do yourself a favor and use Verilog instead. I understand that VHDL forces you to write cleaner code, but it's also frustrating for no good reason. Also, start looking into pipelining ASAP. Implement one micro-arch, benchmark it, then try to do better. It's a great way to learn.
My best advice: synthesize early and often, and spend the time to poke around in the synthesis schematic viewer - Webpack still includes this I believe. It's a great way to compare what you wrote in code to the logic you intended to implement in your mind's eye (or better yet, your notebook).
Please do yourself a favor and use Verilog instead. I understand that VHDL forces you to write cleaner code, but it's also frustrating for no good reason. Also, start looking into pipelining ASAP. Implement one micro-arch, benchmark it, then try to do better. It's a great way to learn.
Building a CPU is what I eventually intend to do and I am curious how would you benchmark a hardware design?
What metrics would someone use for judging the effectiveness of a CPU arch? My current understanding is gate count, area occupied by the design, clocks per instruction (CPI) and maximum frequency the design can be clocked at.
If someone like to try VHDL or Verilog and not have FPGA board, could try EDA Playground : http://www.edaplayground.com/x/Cs2 (An 32 bit ALU)
If someone like to try VHDL or Verilog and not have FPGA board, could try EDA Playground : http://www.edaplayground.com/x/Cs2 (An 32 bit ALU)
This is amazing! I've been looking for an online HDL for learning and trying out ideas on the fly and with no IDE at hand. Thanks for the link!
I have plans for eventually build a VHDL implementation of TR3200 CPU with it.
"Moxie is a general purpose bi-endian load-store processor, with sixteen 32-bit general purpose registers and a comprehensive ISA consisting of two-operand variable width instructions. There are moxie implementations that run on both Altera and Xilinx FPGA architectures, a number of simulator ports (including QEMU), and a complete GNU toolchain for C/C++ development."