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Logicly: a logic gate simulator

joshblog.net

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Re: Logicly: a logic gate simulator

#21

Post by duskwuff »

zhyder wrote: post #12
duskwuff wrote: post #11

Earlier quoted context omitted.

You can simulate a flop with a pair of cross-linked NOR gates.

That would be an SR flop, which -like the JK one- is taught in academia but hardly (if ever) used in industry. I was referring to the edge-triggered D flop; it can also be built from gates but it should be a primitive element. If the object was to have the minimum number of primitive elements in the library, you'd need only a NAND or a NOR gate.

As long as they gave you the ability to compose elements, I'd be all over a circuit simulator that started out with nothing but NAND gates. :)

Re: Logicly: a logic gate simulator

#22

Post by joshtynjala »

duskwuff wrote: post #10
ghshephard wrote: post #2

I wonder how many of us will immediately try to feed a gate back on itself... (Firefox Hung when Flash came face-to-face with infinity, I had to kill -9 it, so be careful) Very cool little App. Has a nice feel for a simple little Logic Gate simulator to play with. Would be nice to see it integrated into: http://www1.idc.ac.il/tecs/

I can't reproduce the problem... it won't let you hook an inverter to itself, but a ring of three inverters works fine (but generates inconsistent output).

Looping should work better now. I pushed a new build.

Re: Logicly: a logic gate simulator

#23

Post by joshtynjala »

sketerpot wrote: post #18
paulgb wrote: post #16

Earlier quoted context omitted.

I'm not sure if it's a bug in this case, but I've used logic simulation software with the same issue and it was considered a "feature". Basically, unconnected nodes of an or-gate are considered HIGH. I suppose it makes more sense when the AND-gate has more inputs. Confused the hell out of me at the time, especially since I had left the assignment to the last possible minute. Edit: remembered the name of the software:…

No, that still doesn't make sense to me. The behavior of a logic circuit with unconnected inputs depends on the implementation; in typical CMOS, those floating inputs can do things as wacky as picking up the electrical fields of nearby people. The proper thing to do with floating inputs is to declare them unknown, and for any logic operation which depends on their values to also be unknown. Most logic simulation soft…

Makes sense. I'll keep that in mind if I make further updates to the simulator.

Re: Logicly: a logic gate simulator

#24

Post by joshtynjala »

sketerpot wrote: post #19

This would be even better if it supported gate delays. If it did, then we could make a ring oscillator by chaining an odd number of NOT gates in a circle, and that would just be so much fun. That sort of simulation is actually easier than it sounds; you just maintain an event queue and add a new event to the queue whenever an input to a gate changes.

A new build has been uploaded. Gates now have a propagation delay.

Re: Logicly: a logic gate simulator

#25

Post by joshtynjala »

zhyder wrote: post #9

If the creator of the tool is reading: 1. Please add support for sequential logic with flops. 2. Minor bug: the "input" and "output" labels are reversed on the left pane.

Arguable on the label reversal. As someone on Reddit explained, "a lightbulb accepts input, and switches and clocks produce output".

Re: Logicly: a logic gate simulator

#26

Post by sketerpot »

joshtynjala wrote: post #24
sketerpot wrote: post #19

This would be even better if it supported gate delays. If it did, then we could make a ring oscillator by chaining an odd number of NOT gates in a circle, and that would just be so much fun. That sort of simulation is actually easier than it sounds; you just maintain an event queue and add a new event to the queue whenever an input to a gate changes.

A new build has been uploaded. Gates now have a propagation delay.

Have I mentioned that you are awesome, and so is Logicly? Because it's true.

Re: Logicly: a logic gate simulator

#27

Post by NonEUCitizen »

Suggestions:

1. Instead of a clickable text field that says "Simulation is STOPPED" , use something obviously clickable (obvious even when mouse is not hovering over it), like a button, and make it say "Start Simulation" . Likewise, instead of "Simulation is ACTIVE" , make the button say "Stop Simulation" . [more specific version of thehickmans' suggestion]

2. Make active the default state, i.e. the button says "Stop Simulation" by default. [seconding psyklic's suggestion]

Re: Logicly: a logic gate simulator

#28

Post by shard »

joshtynjala wrote: post #25
zhyder wrote: post #9

If the creator of the tool is reading: 1. Please add support for sequential logic with flops. 2. Minor bug: the "input" and "output" labels are reversed on the left pane.

Arguable on the label reversal. As someone on Reddit explained, "a lightbulb accepts input, and switches and clocks produce output".

You can argue that, but to digital circuit designers, switches and clocks are inputs to the system you are designing, and light bulbs and LEDs are outputs of the system. This is going against convention.

Re: Logicly: a logic gate simulator

#29

Post by shard »

duskwuff wrote: post #21
zhyder wrote: post #12

Earlier quoted context omitted.

That would be an SR flop, which -like the JK one- is taught in academia but hardly (if ever) used in industry. I was referring to the edge-triggered D flop; it can also be built from gates but it should be a primitive element. If the object was to have the minimum number of primitive elements in the library, you'd need only a NAND or a NOR gate.

As long as they gave you the ability to compose elements, I'd be all over a circuit simulator that started out with nothing but NAND gates. :)

Wooo that would feel like writing a C program starting with assembly...

Re: Logicly: a logic gate simulator

#30

Post by duskwuff »

joshtynjala wrote: post #22
duskwuff wrote: post #10

Earlier quoted context omitted.

I can't reproduce the problem... it won't let you hook an inverter to itself, but a ring of three inverters works fine (but generates inconsistent output).

Looping should work better now. I pushed a new build.

Odd-length loops of inverters still end up making one of the inverters enter an inconsistent state.

(Edit: never mind, a shift-reload does wonders. Bravo!)

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