If the creator of the tool is reading: 1. Please add support for sequential logic with flops. 2. Minor bug: the "input" and "output" labels are reversed on the left pane.
You can simulate a flop with a pair of cross-linked NOR gates.
Logicly: a logic gate simulator
11–20 of 32 posts
Re: Logicly: a logic gate simulator
#12If the creator of the tool is reading: 1. Please add support for sequential logic with flops. 2. Minor bug: the "input" and "output" labels are reversed on the left pane.
You can simulate a flop with a pair of cross-linked NOR gates.
That would be an SR flop, which -like the JK one- is taught in academia but hardly (if ever) used in industry. I was referring to the edge-triggered D flop; it can also be built from gates but it should be a primitive element. If the object was to have the minimum number of primitive elements in the library, you'd need only a NAND or a NOR gate.
Re: Logicly: a logic gate simulator
#13Pretty cool. I think I semi-broke it (or at least found a bug):
http://marcusvorwaller.com/look/Mozilla_Firefox-20090503-095...
Re: Logicly: a logic gate simulator
#14That is fun to play with! It reminds me of Circuit Simulator? from the MacPlus days.
I think you should make the simulator stopped/active control more obvious.
Re: Logicly: a logic gate simulator
#15Would be really cool if one could define "new gates" in terms of gates, e.g. a half-adder, a full-adder.
agreed. a couple slots for your own black boxing of a component would enable fairly complex ideas to be quickly demonstrated. Could be a great teaching tool.
Indeed. In the CS architecture class here they use Logic Works, which is only a little higher-level, but with a much worse interface.
It is no replacement for more powerful things (e.g. FPGAdvantage), but for didactic purposes, this is quite useful.
Re: Logicly: a logic gate simulator
#16Pretty cool. I think I semi-broke it (or at least found a bug): http://marcusvorwaller.com/look/Mozilla_Firefox-20090503-095...
I'm not sure if it's a bug in this case, but I've used logic simulation software with the same issue and it was considered a "feature". Basically, unconnected nodes of an or-gate are considered HIGH. I suppose it makes more sense when the AND-gate has more inputs.
Confused the hell out of me at the time, especially since I had left the assignment to the last possible minute.
Edit: remembered the name of the software: http://ozark.hendrix.edu/~burch/logisim/
Re: Logicly: a logic gate simulator
#17I wish it had a tri-state buffer.
Re: Logicly: a logic gate simulator
#18Pretty cool. I think I semi-broke it (or at least found a bug): http://marcusvorwaller.com/look/Mozilla_Firefox-20090503-095...
I'm not sure if it's a bug in this case, but I've used logic simulation software with the same issue and it was considered a "feature". Basically, unconnected nodes of an or-gate are considered HIGH. I suppose it makes more sense when the AND-gate has more inputs. Confused the hell out of me at the time, especially since I had left the assignment to the last possible minute. Edit: remembered the name of the software:…
No, that still doesn't make sense to me. The behavior of a logic circuit with unconnected inputs depends on the implementation; in typical CMOS, those floating inputs can do things as wacky as picking up the electrical fields of nearby people. The proper thing to do with floating inputs is to declare them unknown, and for any logic operation which depends on their values to also be unknown. Most logic simulation software I've used or written has worked this way.
Re: Logicly: a logic gate simulator
#19This would be even better if it supported gate delays. If it did, then we could make a ring oscillator by chaining an odd number of NOT gates in a circle, and that would just be so much fun. That sort of simulation is actually easier than it sounds; you just maintain an event queue and add a new event to the queue whenever an input to a gate changes.
Re: Logicly: a logic gate simulator
#20Earlier quoted context omitted.
I'm not sure if it's a bug in this case, but I've used logic simulation software with the same issue and it was considered a "feature". Basically, unconnected nodes of an or-gate are considered HIGH. I suppose it makes more sense when the AND-gate has more inputs. Confused the hell out of me at the time, especially since I had left the assignment to the last possible minute. Edit: remembered the name of the software:…
No, that still doesn't make sense to me. The behavior of a logic circuit with unconnected inputs depends on the implementation; in typical CMOS, those floating inputs can do things as wacky as picking up the electrical fields of nearby people. The proper thing to do with floating inputs is to declare them unknown, and for any logic operation which depends on their values to also be unknown. Most logic simulation soft…
Thanks. Now I feel justified in thinking it was a dumb "feature" at the time. :)