The 6502 CPU's overflow flag explained at the silicon level
21–30 of 34 posts
Re: The 6502 CPU's overflow flag explained at the silicon level
#22Earlier quoted context omitted.
I recall waiting a couple of minutes for my computer to just boot in the 80s. When I want to use my phone, it becomes usable in well under a second. Waiting a few seconds every time I hit save was fun. Didn't stop me from developing a ferocious ^S reflex. Fortunately, save is fast enough not to be noticeable these days, to the extent that it usually happens automatically now. Watching a WYSIWYG font menu draw each in…
I don't know what you were using but I was booted and operational in under 3-4 seconds on everything I used in the 80s (BBC Master, Acorn A310)
Re: The 6502 CPU's overflow flag explained at the silicon level
#23Earlier quoted context omitted.
If you want to add 2 32-bit integers, on 6502 you'll need something like the following, assuming this is a 32-bit integer you're actively working with and are probably about to use again fairly soon: CLC ; 2 LDA&70 ADC&74 STA&70 ; 3 3 3 = 9 LDA&71 ADC&75 STA&71 ; 3 3 3 = 9 LDA&72 ADC&76 STA&72 ; 3 3 3 = 9 LDA&73 ADC&77 STA&73 ; 3 3 3 = 9 That's for a total of 38 cycles. So on the computer I started programming on, yo…
And that's loading/storing to/from the zero page (the first 256 bytes of memory). Loading/storing from higher addresses requires 4 cycles. But, "ADD ESI,EDX" is adding two registers isn't it? So I think you need to include the loading/storing of those registers back to memory for a more fair comparison. I haven't touched 6502 assembly in over 20 years. Brings back memories. :-)
Re: The 6502 CPU's overflow flag explained at the silicon level
#24Very interesting And this is 30 year old tech. The 6502, the processor in you cell phone is about 1000x faster than it (and much more capable) To me the hardest part (apparently) is converting the electronic circuit to the actual chip drawings. Not sure how this is done (how do you route it). And this was done by hand in the 6502, the drawings were done the size of a desk and reduced photographically. (IIRC)
Almost 38 years, even... If you're interested in the story around MOS and the 6502, the early parts of "Commodore: A Company on the Edge" by Brian Bagnall covers it quite a bit including parts about the manual layout work that Bill Mensch did. Here's an article about it too: http://research.swtch.com/6502 Not only did they route / layout by hand-drawing, and then cut the Rubylith photomask by hand (it's not a drawing…
I've seen that story before that the 6502 worked perfectly the first time, but I think there's some mythologizing going on. The ROR instruction was totally broken on the first release of the 6502 and wasn't fixed until months later. [1]
The quote above says that the 6502 has 3510 transistors, and this number appears many other places. It turns out that the 6502 has 3510 enhancement transistors and 1018 depletion transistors, for a total of 4528 transistors, according to the visual6502 analysis.
And if you're interested in the inner workings of the 6502, you should definitely check out the huge transistor-level schematic at: http://www.downloads.reactivemicro.com/Public/Electronics/CP...
[1] http://en.wikipedia.org/wiki/6502#Bugs_and_quirks and details at http://www.pagetable.com/?p=406
Re: The 6502 CPU's overflow flag explained at the silicon level
#25Earlier quoted context omitted.
How did you come up with 1000x? With Moore's law we are only 3 orders of magnitude better than a processor from the late 1970s?
The x1000 is a huge understatement. For example these days CPUs are much more optimal in terms of cycles per instruction and inversely instructions per cycle . Back then when multiplication of two word-sized(8 bits back then) values took 24 cycles, these days we can do that in 12 cycles for 64-bit values. Because of superscalar processing and thus instruction level parallelism, we can typically do 2-4 ALU operations…
Re: The 6502 CPU's overflow flag explained at the silicon level
#26Earlier quoted context omitted.
Not to mention further performance advancements in processor design since then (pipelining, SIMD, etc...), further increasing throughput above the 1000x threshold. One should also consider the increases in word length, adding the ability to process more data in less time.
If you want to add 2 32-bit integers, on 6502 you'll need something like the following, assuming this is a 32-bit integer you're actively working with and are probably about to use again fairly soon: CLC ; 2 LDA&70 ADC&74 STA&70 ; 3 3 3 = 9 LDA&71 ADC&75 STA&71 ; 3 3 3 = 9 LDA&72 ADC&76 STA&72 ; 3 3 3 = 9 LDA&73 ADC&77 STA&73 ; 3 3 3 = 9 That's for a total of 38 cycles. So on the computer I started programming on, yo…
You're even playing nice against the 6502, you're using a simple add, now compare with SIMD instructions
Re: The 6502 CPU's overflow flag explained at the silicon level
#27Earlier quoted context omitted.
Almost 38 years, even... If you're interested in the story around MOS and the 6502, the early parts of "Commodore: A Company on the Edge" by Brian Bagnall covers it quite a bit including parts about the manual layout work that Bill Mensch did. Here's an article about it too: http://research.swtch.com/6502 Not only did they route / layout by hand-drawing, and then cut the Rubylith photomask by hand (it's not a drawing…
I'm glad to see the 6502 getting so much attention on HN. I like the article title Unwind used here, so I've changed the article's original title to match. (Note to self: try to come up with better titles.) I've seen that story before that the 6502 worked perfectly the first time, but I think there's some mythologizing going on. The ROR instruction was totally broken on the first release of the 6502 and wasn't fixed…
Re: The 6502 CPU's overflow flag explained at the silicon level
#28Earlier quoted context omitted.
Almost 38 years, even... If you're interested in the story around MOS and the 6502, the early parts of "Commodore: A Company on the Edge" by Brian Bagnall covers it quite a bit including parts about the manual layout work that Bill Mensch did. Here's an article about it too: http://research.swtch.com/6502 Not only did they route / layout by hand-drawing, and then cut the Rubylith photomask by hand (it's not a drawing…
I'm glad to see the 6502 getting so much attention on HN. I like the article title Unwind used here, so I've changed the article's original title to match. (Note to self: try to come up with better titles.) I've seen that story before that the 6502 worked perfectly the first time, but I think there's some mythologizing going on. The ROR instruction was totally broken on the first release of the 6502 and wasn't fixed…
http://www.kickstarter.com/projects/textfiles/the-jason-scot...
Re: The 6502 CPU's overflow flag explained at the silicon level
#29Earlier quoted context omitted.
How did you come up with 1000x? With Moore's law we are only 3 orders of magnitude better than a processor from the late 1970s?
Wikipedia lists the 6502 as having between 1 MHz to 2 MHz and the Samsung Galaxy SII as having around 1.2 GHz.[0] I'm guessing that's where the 1000x comes from... Or, you know, it's just a nice big number. ;P [0] Of course, that's ignoring multiple cores, better microcode, caches, etc.
Re: The 6502 CPU's overflow flag explained at the silicon level
#30Earlier quoted context omitted.
And that's loading/storing to/from the zero page (the first 256 bytes of memory). Loading/storing from higher addresses requires 4 cycles. But, "ADD ESI,EDX" is adding two registers isn't it? So I think you need to include the loading/storing of those registers back to memory for a more fair comparison. I haven't touched 6502 assembly in over 20 years. Brings back memories. :-)
This is working data, so you'd keep it in a register if possible. Sadly that just happens not to be possible on the 6502 :)
CLC ; 2
ADC #b1 STA&70 ; 0 2 3 = 5
LDA #a2 ADC #b2 TAY ; 2 2 2 = 6
LDA #a3 ADC #b3 TAX ; 2 2 2 = 6
LDA #a4 ADC #b4 ; 2 2 = 4
; total 23 cycles