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Sophon PFG-1: a monolithic-3D AI ASIC with 330 GB of on-die DRAM and no HBM

phantafield.com

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Re: Sophon PFG-1: a monolithic-3D AI ASIC with 330 GB of on-die DRAM and no HBM

#21

Post by binyu »

matt123456789 wrote: post #19
minkowsky wrote: post #9

Earlier quoted context omitted.

Author here. Thanks! Short version: Cerebras and we are attacking the same memory wall from opposite axes — they scale out in 2D, we scale up in 3D. Cerebras WSE-3 is a brilliant packaging play: one wafer-scale chip (~46,000 mm², ~900k cores) with ~44 GB of SRAM spread across the plane, so compute and memory sit side by side with enormous bandwidth. The catch is density — SRAM is a 6T cell, so even a whole wafer only…

I suspect you are being downvoted because your answer is AI-generated, but I found it very clear and will upvote.

What makes you think his reply was AI generated?

Edit: I can see a bunch of hints, most definitely. Still a good comment though.

Re: Sophon PFG-1: a monolithic-3D AI ASIC with 330 GB of on-die DRAM and no HBM

#22

Post by minkowsky »

vessenes wrote: post #12

Minkowsky, cool design! Question - the ASIC designers I've worked with over the years have been fairly adamant that integrating memory on package interspersed with logic is very difficult; the general statements run like "those designs always look great on paper, but never tape out properly". Have you done any hardware tests of this plan? Is this still considered quality advice? Second q, why start with 28nm? Is the…

Due to the thermal budget, most of the silicon design is constrained to a 2D layout. So the Memory is competing with logic for layout. Now we stack logic in the backend between metals.

We fabricated 2T0C DRAM arrays with a 3D monolithic structure. That's a must-do.

Why 28nm? Because it's cheap, widely available, and already gives us enough performance to beat Nvidia Vera Rubin. We have a road map, scaling it down. https://www.phantafield.com/whitepaper#6-scaling-roadmap

Re: Sophon PFG-1: a monolithic-3D AI ASIC with 330 GB of on-die DRAM and no HBM

#23

Post by wmf »

minkowsky wrote: post #5
wmf wrote: post #4

This design is absolutely wild. It probably won't work but I admire the dream.

Author here. The economy is more realistic than the wafer-scale ASIC by Cerebras.

I'm questioning technical risks such as BEOL transistors and 2T DRAM cell structure, not the economics. Cerebras has already retired their technical risk.

Re: Sophon PFG-1: a monolithic-3D AI ASIC with 330 GB of on-die DRAM and no HBM

#24

Post by vessenes »

gfody wrote: post #17
vessenes wrote: post #12

Minkowsky, cool design! Question - the ASIC designers I've worked with over the years have been fairly adamant that integrating memory on package interspersed with logic is very difficult; the general statements run like "those designs always look great on paper, but never tape out properly". Have you done any hardware tests of this plan? Is this still considered quality advice? Second q, why start with 28nm? Is the…

isn't cerebras the pudding proof of this design? it seems like ai chips galore are appearing from the woodwork but cerebras is 10 years down this rabbit hole and poised to dominate

I believe cerebras is one wafer, not deeply stacked, each core is like half memory half compute by area.

Re: Sophon PFG-1: a monolithic-3D AI ASIC with 330 GB of on-die DRAM and no HBM

#25

Post by minkowsky »

binyu wrote: post #21
matt123456789 wrote: post #19

Earlier quoted context omitted.

I suspect you are being downvoted because your answer is AI-generated, but I found it very clear and will upvote.

What makes you think his reply was AI generated? Edit: I can see a bunch of hints, most definitely. Still a good comment though.

I do use AI for some of the answers. I now know the penalty. Thank you for the heads up.

Re: Sophon PFG-1: a monolithic-3D AI ASIC with 330 GB of on-die DRAM and no HBM

#26

Post by minkowsky »

binyu wrote: post #20
minkowsky wrote: post #9

Earlier quoted context omitted.

Author here. Thanks! Short version: Cerebras and we are attacking the same memory wall from opposite axes — they scale out in 2D, we scale up in 3D. Cerebras WSE-3 is a brilliant packaging play: one wafer-scale chip (~46,000 mm², ~900k cores) with ~44 GB of SRAM spread across the plane, so compute and memory sit side by side with enormous bandwidth. The catch is density — SRAM is a 6T cell, so even a whole wafer only…

> they scale out in 2D, we scale up in 3D. This actually helps a lot, thanks. > Instead of spreading SRAM across a wafer, we stack DRAM on top of the logic Is this done with current manufacturing technologies? Does it require a special process? > no streaming, no off-chip memory at all. ~1 kW, not 23 kW Is this for an individual compute unit? Compared to Cerebras, what's the ratio of power used vs compute output?

I think you are asking for the Energy/token. Cerebras is 12.8J, Sophon is 25.8mJ. Three orders of difference.

Re: Sophon PFG-1: a monolithic-3D AI ASIC with 330 GB of on-die DRAM and no HBM

#27

Post by minkowsky »

addaon wrote: post #8

Since when are we doing 32-layer planar transistor logic on a single chip? Even ignore the use of FETs for eDRAM… I didn’t realize we had decent logic density possible on BEOL.

Because we can put FET on any layer. Usually, BEOL doesn't need such high density. The density depends on what lithography tool and mask you pick.

Re: Sophon PFG-1: a monolithic-3D AI ASIC with 330 GB of on-die DRAM and no HBM

#28

Post by throwaway89201 »

The entire design looks very interesting, but from the outside and without domain expertise I find it very hard to assess if anything about this is actually real or just a large and well-executed product of an AI psychosis.

The signs that this project is real are hard to verify:

- Angel investment by FinFET inventor Chenming Hu [1] seems a big vote of confidence, but there is no independent confirmation of this anywhere, except for two photo's in LinkedIn posts [2], which do look convincing.

- The NanoGalaxy PPMOCVD was presented at IEDM 2025 [3][4], but nobody seems to have written about it except the company itself. In this case, presenting means a poster presentation with a very vibrantly colored marketing picture.

- The NanoGalaxy PPMOCVD is built and in production, because you can "Witness a full 12-inch MoS₂ growth cycle on your own wafer lot" [5], but nobody has reported on this. A photo/video of the actual device would help a lot, but instead a very clean picture of what seems like a 3d-model is shown.

There are a few worrying signs:

- The submitter on HN presents itself as the founder. They have previously submitted other projects under the Phanta or PhantaField names [6]. Notably two hype cycle subjects: DAOs, NFTs and augmented reality, combined in a book that itself is rather 'out there' [7].

- The comments on HN by the founder are clearly AI generated with phrases like "honest caveat". The content seems to make sense (to a non-expert like me), but it's quite jarring.

- All the work except the NanoGalaxy seems to be theoretical for now, but written in very definitive language in extreme detail. For example "The die is built" with specific properties but then referencing three very experimental papers. This can of course be genuine (technical) marketing, but it's also very similar to AI psychosis work that I've encountered elsewhere. Although I must say in comparison this does look a lot more internally consistent and logical to me.

- I find it very hard to believe that the NanoGalaxy is actually existing and working hardware ready to "Witness a full 12-inch MoS₂ growth cycle on your own wafer lot". I would imagine you need a sizable team to produce such a new device, and that seems to be inconsistent with the way the company presents itself (a one man show of the founder). The absence of any verification or showcases of the device, or any evidence of a larger team make it suspect.

[1] https://www.phantafield.com/news/first-angel-investment-chen...

[2] https://www.linkedin.com/feed/update/urn:li:activity:7126002... and https://www.linkedin.com/posts/xuejunxie_its-a-great-honor-t...

[3] https://www.linkedin.com/feed/update/urn:li:share:7404253323...

[4] https://www.phantafield.com/news/12-inch-ppmocvd-iedm-2025

[5] https://www.phantafield.com/product/ppmocvd

[6] https://news.ycombinator.com/submitted?id=minkowsky

[7] https://xcancel.com/thepantheonai

Re: Sophon PFG-1: a monolithic-3D AI ASIC with 330 GB of on-die DRAM and no HBM

#29

Post by minkowsky »

throwaway89201 wrote: post #28

The entire design looks very interesting, but from the outside and without domain expertise I find it very hard to assess if anything about this is actually real or just a large and well-executed product of an AI psychosis. The signs that this project is real are hard to verify: - Angel investment by FinFET inventor Chenming Hu [1] seems a big vote of confidence, but there is no independent confirmation of this anywh…

I also have another side project, thepantheon.ai. I think it's ok to have multiple talents. To make the world a much more interesting place.

We talk to fabs. I am not allowed to expose any conversation. We don't need to prove to average Joe what we have.

It's indeed teamwork to bring it into production, even with huge help from AI. It also takes expertise to make sure AI is correct. As a founder, it's more of a merit than a drawback to create with a minimum headcount.

Re: Sophon PFG-1: a monolithic-3D AI ASIC with 330 GB of on-die DRAM and no HBM

#30

Post by minkowsky »

wmf wrote: post #23
minkowsky wrote: post #5

Earlier quoted context omitted.

Author here. The economy is more realistic than the wafer-scale ASIC by Cerebras.

I'm questioning technical risks such as BEOL transistors and 2T DRAM cell structure, not the economics. Cerebras has already retired their technical risk.

It's risky, like landing a rocket, but not impossible.
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