This design is absolutely wild. It probably won't work but I admire the dream.
Author here. The economy is more realistic than the wafer-scale ASIC by Cerebras.
Can you explain why?
Sophon PFG-1: a monolithic-3D AI ASIC with 330 GB of on-die DRAM and no HBM
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Re: Sophon PFG-1: a monolithic-3D AI ASIC with 330 GB of on-die DRAM and no HBM
#12Minkowsky, cool design! Question - the ASIC designers I've worked with over the years have been fairly adamant that integrating memory on package interspersed with logic is very difficult; the general statements run like "those designs always look great on paper, but never tape out properly".
Have you done any hardware tests of this plan? Is this still considered quality advice?
Second q, why start with 28nm? Is the idea that you want to stick with TSMC and be able to shrink? If this does in fact work well, I can imagine wanting to shoot for a smaller process node pretty quickly. Is there some sort of tech / design gap you'll need to figure out as you go?
Re: Sophon PFG-1: a monolithic-3D AI ASIC with 330 GB of on-die DRAM and no HBM
#13MoS2 lattice construction?
Re: Sophon PFG-1: a monolithic-3D AI ASIC with 330 GB of on-die DRAM and no HBM
#14I've been wondering how long before RAM is fabbed on die to get around supply issues. This is one of the first I've read of so far. How long before Apple releases a CPU with ram on die?
They're typically manufactured with very different processes so one has to wonder what compromises are being made here to get both on the same die.
Re: Sophon PFG-1: a monolithic-3D AI ASIC with 330 GB of on-die DRAM and no HBM
#15Earlier quoted context omitted.
Author here. The economy is more realistic than the wafer-scale ASIC by Cerebras.
Can you explain why?
I have a detailed comparison with Cerebras in economic analysis:
https://www.phantafield.com/whitepaper#7-economic-analysis
Re: Sophon PFG-1: a monolithic-3D AI ASIC with 330 GB of on-die DRAM and no HBM
#16[deleted]
Re: Sophon PFG-1: a monolithic-3D AI ASIC with 330 GB of on-die DRAM and no HBM
#17Minkowsky, cool design! Question - the ASIC designers I've worked with over the years have been fairly adamant that integrating memory on package interspersed with logic is very difficult; the general statements run like "those designs always look great on paper, but never tape out properly". Have you done any hardware tests of this plan? Is this still considered quality advice? Second q, why start with 28nm? Is the…
isn't cerebras the pudding proof of this design? it seems like ai chips galore are appearing from the woodwork but cerebras is 10 years down this rabbit hole and poised to dominate
Re: Sophon PFG-1: a monolithic-3D AI ASIC with 330 GB of on-die DRAM and no HBM
#18[deleted]
Re: Sophon PFG-1: a monolithic-3D AI ASIC with 330 GB of on-die DRAM and no HBM
#19Earlier quoted context omitted.
Hello, kudos for the tremendous work. Could you explain the difference between your design and Cerebras? Bests
Author here. Thanks! Short version: Cerebras and we are attacking the same memory wall from opposite axes — they scale out in 2D, we scale up in 3D. Cerebras WSE-3 is a brilliant packaging play: one wafer-scale chip (~46,000 mm², ~900k cores) with ~44 GB of SRAM spread across the plane, so compute and memory sit side by side with enormous bandwidth. The catch is density — SRAM is a 6T cell, so even a whole wafer only…
I suspect you are being downvoted because your answer is AI-generated, but I found it very clear and will upvote.
Re: Sophon PFG-1: a monolithic-3D AI ASIC with 330 GB of on-die DRAM and no HBM
#20Earlier quoted context omitted.
Hello, kudos for the tremendous work. Could you explain the difference between your design and Cerebras? Bests
Author here. Thanks! Short version: Cerebras and we are attacking the same memory wall from opposite axes — they scale out in 2D, we scale up in 3D. Cerebras WSE-3 is a brilliant packaging play: one wafer-scale chip (~46,000 mm², ~900k cores) with ~44 GB of SRAM spread across the plane, so compute and memory sit side by side with enormous bandwidth. The catch is density — SRAM is a 6T cell, so even a whole wafer only…
> they scale out in 2D, we scale up in 3D.
This actually helps a lot, thanks.
> Instead of spreading SRAM across a wafer, we stack DRAM on top of the logic
Is this done with current manufacturing technologies? Does it require a special process?
> no streaming, no off-chip memory at all. ~1 kW, not 23 kW
Is this for an individual compute unit? Compared to Cerebras, what's the ratio of power used vs compute output?