21–30 of 62 posts
The most unhinged AVX-512 instruction is GF2P8AFFINEQB.
There's a pretty good list of weird off-label uses for the Galois Field instructions here: https://gist.github.com/animetosho/d3ca95da2131b5813e16b5bb1...
The most unhinged AVX-512 instruction is GF2P8AFFINEQB.
From my 1980s 8-bit CPU perspective, the instruction is unhinged based solely on the number of letters. Compared to LDA, STA, RTS, that's not an assembler mnemonic, it's a novel. :-)
vs
"Galois Field 2^8 affine transform on quad binary words" (GF2P8AFFINEQB)
The compression factor isn't quite the same on character count, but it's still abbreviated. :)
mary:
docs:
- 0:
posns: [0, 8]
- 1:
posns: [2]
- 3:
posns: [1]Earlier quoted context omitted.
It's a shame that Intel seemed to really not want people to use it, given they started disabling the ability to use it in future microcode, and fused it off in later parts.
> It's a shame that Intel seemed to really not want people to use it AVX-512 was never part of the specification for those CPUs. It was never advertised as a feature or selling point. You had to disable the E cores to enable AVX-512, assuming your motherboard even supported it. Alder Lake AVX-512 has reached mythical status, but I think the number of people angry about it is far higher than the number of people who e…
Is the first example under The genius idea heading missing entry #3 below? mary: docs: - 0: posns: [0, 8] - 1: posns: [2] - 3: posns: [1]
> The inverted index will look something like this:
He isn't wrong. It is indeed "something like".
Earlier quoted context omitted.
It's a shame that Intel seemed to really not want people to use it, given they started disabling the ability to use it in future microcode, and fused it off in later parts.
> It's a shame that Intel seemed to really not want people to use it AVX-512 was never part of the specification for those CPUs. It was never advertised as a feature or selling point. You had to disable the E cores to enable AVX-512, assuming your motherboard even supported it. Alder Lake AVX-512 has reached mythical status, but I think the number of people angry about it is far higher than the number of people who e…
The Intel-AMD x86-64 architecture is full of horrible things, starting with the System Management Mode added in 1990, which have been added by Intel only because every time Microsoft has refused to update Windows, expecting that the hardware vendors must do the work instead of Microsoft for enabling Windows to continue to work on newer hardware, even when that causes various disadvantages for the customers.
Moreover, even if Intel had not said that Alder Lake will support AVX-512, they also had not said that the P-cores of Alder Lake will not support AVX-512.
Therefore everybody had expected that Intel will continue to provide backward compatibility, as always before that, so the P-cores of Alder Lake will continue to support any instruction subset that had been supported by Rocket Lake and Tiger Lake and Ice Lake and Cannon Lake.
The failure to be compatible with their previous products has been a surprise for everybody.
Earlier quoted context omitted.
> It's a shame that Intel seemed to really not want people to use it AVX-512 was never part of the specification for those CPUs. It was never advertised as a feature or selling point. You had to disable the E cores to enable AVX-512, assuming your motherboard even supported it. Alder Lake AVX-512 has reached mythical status, but I think the number of people angry about it is far higher than the number of people who e…
They had to disable AVX-512 only because Microsoft was too lazy to rewrite their thread scheduler to handle heterogeneous CPU cores. The Intel-AMD x86-64 architecture is full of horrible things, starting with the System Management Mode added in 1990, which have been added by Intel only because every time Microsoft has refused to update Windows, expecting that the hardware vendors must do the work instead of Microsoft…
Thus, SMM, because there was no other way to hook power management on a 386 laptop running " normal" DOS
The most unhinged AVX-512 instruction is GF2P8AFFINEQB.
What about GF2P8AFFINEINVQB?
The only case where I've had use of GF(2^8) inverses is in FEC algorithms (Forney's algorithm) and then you need some kind of weird polynomial. But all of those needs are rarely in the hot-path, and the FEC algo's are way outdated
Earlier quoted context omitted.
What about GF2P8AFFINEINVQB?
It has a fixed polynomial, so not really that useful for anything but AES The only case where I've had use of GF(2^8) inverses is in FEC algorithms (Forney's algorithm) and then you need some kind of weird polynomial. But all of those needs are rarely in the hot-path, and the FEC algo's are way outdated
The most unhinged AVX-512 instruction is GF2P8AFFINEQB.