Yeah uh if you think microcontrollers are on 3nm... No. Most microcontrollers are on 28-40 if not larger. Lower gate widths can sometimes increase logic density and sometimes fmax but they dramatically increase static power, yields, and by extension cost (along with the other factors as outlined by your ieee source).
This gross look shows what I believe are some PCIe block die areas.
https://substackcdn.com/image/fetch/f_auto,q_auto:good,fl_pr...
This is roughly half the size of what I've seen to be some of the smallest micros, and those are most likely not on the same lithographies. When you combine the amount of additional RAM/ROM needed to run a PCIe stack, maybe divide by 4 for 1 lane instead of 4 to be generous, you're still likely going to double the die area used. On top of that which I didn't mention earlier is that PCIe transceivers are going to need more per supply circuity. ST's been doing a good job of integrating things in for stuff like DSI but those app notes show more complexity than the aforementioned atmega328p which is so simple it can sometimes be run without decoupling caps on a breadboard.
If you look at die shots for micros, a lot of the time you'll see most of the area is consumed by large arrays of SRAM or flash. And SRAM is known to not scale to lower lithographies. So, I don't expect to see this changing really. To be PCIe compliant you'll likely need to have the ability to store a full TLP. On a 328p, that could double if not more the SRAM needed. So the chip would get idk ballpark 3x bigger with all the stuff included? I just don't see manufacturers wanting to do this, which is likely why they haven't. There are very few cortex M chips with PCIe that come to mind. Some more cortex Rs. I figure if it was really the silver bullet, somebody would've done it by this point.
