I'm not familiar with the other standards this is being compared to. Why not use PCIe?
I think you missed the "low-cost" part from the title.
Why is PCIe expensive?
Syzygy: An open standard for low cost, compact and high-performance peripherals
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Re: Syzygy: An open standard for low cost, compact and high-performance peripherals
#12I'm not familiar with the other standards this is being compared to. Why not use PCIe?
2 primary reasons come to mind:
1. PCIe is mostly transceivers. Syzygy can be low speed, single ended, etc etc as well.
2. PCIe's card edge connectors can add manufacturing cost (gold plating, chamfered edges, board thickness tricks, etc) and are also relatively large.
Re: Syzygy: An open standard for low cost, compact and high-performance peripherals
#13random rant not really related to op but spurred by it: i know it will probably never happen, but it would be 'truly epic' if hard PCIe endpoints became as ubiquitous as say, SPI peripheral blocks, within MCUs/MPUs and the general silicon jelly-bean world. just a very high speed, very low latency, very widespread, very standard, very boring communication channel. and ofcourse an atmega328p can't keep up with the full…
I'm hoping UCIe starts to fix this. It's touted as being something that can combine the low power with the high speed. As is PCIe is a relatively high power for anything that doesn't need the speed. You need to be moving pretty well past normal MCU interfaces (spi, uart, etc) before you see the power trade off.
As is, PCIe would add sizable die area consumption, raise power consumption by an order of magnitude, and likely raise part cost dramatically. Couple this with cheapy board designs that often can't even get USB 1.0-2.0 right (recalling the amount of boards that get the pull up resistors or power supply schema wrong), and it sounds like a nightmare to manage.
I think gigabit Ethernet is where I'd prefer the effort spent. Most micros have at most 100 Mb. NXP's i.MX RT line has gigabit but that's the only one I know of.
Re: Syzygy: An open standard for low cost, compact and high-performance peripherals
#14I'm not familiar with the other standards this is being compared to. Why not use PCIe?
2 primary reasons come to mind: 1. PCIe is mostly transceivers. Syzygy can be low speed, single ended, etc etc as well. 2. PCIe's card edge connectors can add manufacturing cost (gold plating, chamfered edges, board thickness tricks, etc) and are also relatively large.
PCIe doesn't have to be over an edge connector. PMC and XMC standards use board-to-board stacking. You can also do PCIe over cabling.
What's the point of low speed single ended I/O into an FPGA module? Seems like a waste of effort.
Re: Syzygy: An open standard for low cost, compact and high-performance peripherals
#15Earlier quoted context omitted.
2 primary reasons come to mind: 1. PCIe is mostly transceivers. Syzygy can be low speed, single ended, etc etc as well. 2. PCIe's card edge connectors can add manufacturing cost (gold plating, chamfered edges, board thickness tricks, etc) and are also relatively large.
PCIe doesn't have to be over an edge connector. PMC and XMC standards use board-to-board stacking. You can also do PCIe over cabling. What's the point of low speed single ended I/O into an FPGA module? Seems like a waste of effort.
> What's the point of low speed single ended I/O into an FPGA module?
Hardware interfacing with the physical world. Driving small numbers of LEDs, h-bridge drivers, load switches, regulator control signals, reading buttons, accelerometers, gyroscopes, magnetometers, PWM controllers, GPS, ...
Re: Syzygy: An open standard for low cost, compact and high-performance peripherals
#16Re: Syzygy: An open standard for low cost, compact and high-performance peripherals
#17Earlier quoted context omitted.
PCIe doesn't have to be over an edge connector. PMC and XMC standards use board-to-board stacking. You can also do PCIe over cabling. What's the point of low speed single ended I/O into an FPGA module? Seems like a waste of effort.
> What's the point of low speed single ended I/O into an FPGA module? Hardware interfacing with the physical world. Driving small numbers of LEDs, h-bridge drivers, load switches, regulator control signals, reading buttons, accelerometers, gyroscopes, magnetometers, PWM controllers, GPS, ...
That's what microcontrollers are for. FPGAs are harder to program and use a lot more power. So the juice needs to be worth the squeeze!
Re: Syzygy: An open standard for low cost, compact and high-performance peripherals
#18Hadn’t expected to see this here! I helped put this standard together while working at Opal Kelly. I think we had some nifty ideas in there (using an analog voltage for peripheral addressing was one of my favorite). It has slowly seen more adoption as time passes. Would always love to see more adoption!
That sounds interesting (analog addressing). Could you expound?
With many of these types of standards (FMC and Syzygy) it becomes helpful to include some form of memory on the peripheral cards. With Syzygy it is required in order to store some helpful data about the card (product name, manufacturer) along with supported voltage ranges for an adjustable voltage rail from the carrier board. FMC used standard off the shelf I2C eeproms for this task, with some pins on the FMC connector used to indicate the address for the particular slot that the peripheral was attached to on the motherboard. We wanted to lose as few pins as possible for address lines on Syzygy, so we opted to instead use a microcontroller with an ADC for our peripheral flash memory. There was a single pin used to indicate the peripheral address. This pin had a fixed resistor to a power rail on the peripheral and the carrier would have a port-specific resistor to ground on the same pin. By reading the voltage across these resistors we defined 16 addresses with just a single pin. IIRC the microcontrollers we selected were almost the same cost as the I2C flash we would have used in their place!
It was a pretty neat hack.
Placing small microcontrollers on the peripherals also opened up other functions like using them for basic power supply sequencing.
Re: Syzygy: An open standard for low cost, compact and high-performance peripherals
#19Earlier quoted context omitted.
2 primary reasons come to mind: 1. PCIe is mostly transceivers. Syzygy can be low speed, single ended, etc etc as well. 2. PCIe's card edge connectors can add manufacturing cost (gold plating, chamfered edges, board thickness tricks, etc) and are also relatively large.
PCIe doesn't have to be over an edge connector. PMC and XMC standards use board-to-board stacking. You can also do PCIe over cabling. What's the point of low speed single ended I/O into an FPGA module? Seems like a waste of effort.
Your question was why to use this over PCIe. Maybe I'm misunderstanding your question but as Syzygy is a connector standard, your question must have been about the connector. I think colloquially the "PCIe connector" refers to the finger and slot standard.
As for why to use single end low speed I/O, I guess it's about perspective. For some, an FPGA is something that sits on a PCIe bus or network. For a lot of people, it's a lot more than that. Something that talks to countless chips that maybe need spi, i2c, uart, or something custom.
For example, think about all those 1 wire LED strips and how it easy it would be to do that in HDL compared to the other approaches. Being and to work easily with bits vs bytes has huge advantages for custom interfaces. Another example: one time a group I was working with wanted to talk to battery management modules. Each one had a uart and they had to get daisy chained together, complicating things a lot. An FPGA with more than a few uarts is trivial and could've talked to each one independently. Even the highest end micros have maybe at most 20. You could fit 16 on 1 of these connectors. The UART block from Xilinx is on the order of 100 flops. You could have literally hundreds of uarts. Not that I have seen a need for that, but who knows, maybe someone does.
Getting rambley but another option is for test devices. Let's say you have a device that has a low speed interface and you want to test a lot of them at a time. You could use a bunch of multiplexors and time division control logic, or slap down an FPGA and do them all at once.
Re: Syzygy: An open standard for low cost, compact and high-performance peripherals
#20Earlier quoted context omitted.
2 primary reasons come to mind: 1. PCIe is mostly transceivers. Syzygy can be low speed, single ended, etc etc as well. 2. PCIe's card edge connectors can add manufacturing cost (gold plating, chamfered edges, board thickness tricks, etc) and are also relatively large.
PCIe doesn't have to be over an edge connector. PMC and XMC standards use board-to-board stacking. You can also do PCIe over cabling. What's the point of low speed single ended I/O into an FPGA module? Seems like a waste of effort.
I think “low speed” is quite a relative term here. PCIe serdes lanes are for very high data rate communication (> 1gbps per lane). This is the realm of the Syzygy XCVR standard.
The lower speed Syzygy standard, while not operating at these speeds, is capable of much higher rates than a typical microcontroller. There are many peripherals with I/O requirements beyond a simple LED or SPI device, but below that of a PCIe or other high rate transceiver such has:
- moderate to high end ADCs and DACs (LVDS and parallel)
- image sensors (LVDS, parallel, and HiSPI)
- various networking PHYs
The lower end syzygy connector has pinouts to support LVDS differential pairs, which can easily achieve hundreds of Mbps data rates.