What does SoC stand for? I’m assuming not Summer of Code.
FPGAs becoming more SoC-like
21–30 of 58 posts
Re: FPGAs becoming more SoC-like
#22Re: FPGAs becoming more SoC-like
#23Article says "CPU does not fit FPGA synthesis very well and uses almost whole thing". People serious about prototyping usually get daughterboards for FPGA and/or FPGA stacks specifically to prototype big things with CPUs. The buses can go outside of main FPGA with CPU and into other things. I know at least one big SoC project which went that way. I also think that having an ARM core in FPGA is a vendor lock in. For e…
> ARM itself is not very nice design from contemporary point of view. [...] they decided to use that ARM thing
ARM CPUs are the de-facto standard in the embedded world (except for simple 8-bit MCUs), so what should Xilinx have done? Design their own, proprietary CPU architecture and ISA? Choose some other architecture with 2% market share? Both paths would have led to the immediate death of the whole product line.
> 1) ARM is not RISC (multiregister load/store execute in several clocks)
So? Who cares?
> 2) too much of initial design of first ARM (which was not planned for longterm evolution) is visible in ISA.
Ah, yes, technological purism – the quickest way to practical irrelevance.
Re: FPGAs becoming more SoC-like
#24Earlier quoted context omitted.
What's the tooling like for a typical, production-quality FPGA project nowadays? Last I checked, which is admittedly a couple of years ago (and I didn't dive in very deeply), it was a horrible mix of badly programmed vendor-specific Windows-only GUI tools. It seemed a lot like the embedded processor market where every single vendor has their own lock-in strategy and the whole ecosystem suffers for it. Has this improv…
All the FPGA tools by Xilinx work well under Linux and Vivado is actually quite pleasant to use. Almost all of the EDA tools can be scripted with TCL (cadence has a host of other DSL aswell) so you don’t need to use the GUI if you don’t want to.
Vivado is absolutely terrible, especially the GUI. Our toolchain at work is set up so that it can be entirely avoided, with developers only writing Verilog in their editor of choice, and calling make or pushing to Jenkins when they want results. And then they go home, as it takes a full day to build a product on our server farm. Sim/others is done with third-party products.
I recall one Xilinx event where a Xilinx presenter asked how many people were using the Vivado IDE for development. IIRC, only a single hand was held up.
Vivado isn't worse than the competition, though. Intel/Altera's offering is also a steaming pile of crap (we evaluate the competing platform every once in a while when we decide what FPGAs to use for new products).
I don't know why all FPGA tooling sucks, but it does.
Re: FPGAs becoming more SoC-like
#25Earlier quoted context omitted.
It wasn't a question. ASIC isn't the tool for large volume, it's the tool for when you can accept a several year turnaround time for revisions, vs. a day or two. ASIC > FPGA... except if your design changes, ever. If anything high-bandwidth or design intensive is going on, you're definitely going to revise your design many times. FPGA's are massively on the rise (although slightly less so than Xilinx would like), and…
What's the tooling like for a typical, production-quality FPGA project nowadays? Last I checked, which is admittedly a couple of years ago (and I didn't dive in very deeply), it was a horrible mix of badly programmed vendor-specific Windows-only GUI tools. It seemed a lot like the embedded processor market where every single vendor has their own lock-in strategy and the whole ecosystem suffers for it. Has this improv…
Well, it certainly hasn't been Windows specific for over a decade, but it's definitely bad.
Comparing it to software development toolchains, one might even go as far as calling it a steaming pile of horsedung. However, a lot of it can be hidden, making the flow: 1. Write verilog in your editor of choice, 2. Call make. 3. Come back tomorrow to check the result.
Re: FPGAs becoming more SoC-like
#26Earlier quoted context omitted.
All the FPGA tools by Xilinx work well under Linux and Vivado is actually quite pleasant to use. Almost all of the EDA tools can be scripted with TCL (cadence has a host of other DSL aswell) so you don’t need to use the GUI if you don’t want to.
Vivado is absolutely terrible, especially the GUI. Our toolchain at work is set up so that it can be entirely avoided, with developers only writing Verilog in their editor of choice, and calling make or pushing to Jenkins when they want results. And then they go home, as it takes a full day to build a product on our server farm. Sim/others is done with third-party products. I recall one Xilinx event where a Xilinx pr…
Writing Verilog in the editor of choice then calling make and pushing to Jenkins sounds amazing. Could you elaborate further on the methods and best practices to develop FPGA without Vivado IDE?(As your story indicate that there are many people can do this in the industry.) I'd like to know more about the setup.
Re: FPGAs becoming more SoC-like
#27Earlier quoted context omitted.
Windows only tools? You must have been using Altera options (I briefly maintained the page for Quartus compatibility at wine, circa 2004). Even them have had Linux support for a while, Xilinx has Linux support for as far as I remember, at least some ten years. The ecosystem is terrible, I agree with you. However, the lock in is restricted for the final synthesis part. Simulation is mostly done with (very expensive) t…
I know someone who’s implemented some string algorithms for FPGA with verilog. Is writing the code distinct from the tooling you’re referring to, or simply an open source flavor of deployment? I haven’t done any FPGA work.
When he talks about Verilog, he is referring to the language used for development and implementation. We're talking about a different part of the chain, something akin to the compiler, make, cmake and alike.
Of course, there's some dynamic between the tool chain and the language itself. For example, it doesn't matter if the language has the coolest feature if the compiler does not support it, and the toolchain will help you manage more complex code safely.
Re: FPGAs becoming more SoC-like
#28Earlier quoted context omitted.
All the FPGA tools by Xilinx work well under Linux and Vivado is actually quite pleasant to use. Almost all of the EDA tools can be scripted with TCL (cadence has a host of other DSL aswell) so you don’t need to use the GUI if you don’t want to.
Vivado is absolutely terrible, especially the GUI. Our toolchain at work is set up so that it can be entirely avoided, with developers only writing Verilog in their editor of choice, and calling make or pushing to Jenkins when they want results. And then they go home, as it takes a full day to build a product on our server farm. Sim/others is done with third-party products. I recall one Xilinx event where a Xilinx pr…
And don't get me started on trying to version control a Vivado project. It's like they didn't even consider the possibility of committing a project to source control! I last used Vivado about 2 years ago but doubt things have changed much. It really makes me wonder how Xilinx does it in-house.
Re: FPGAs becoming more SoC-like
#29Earlier quoted context omitted.
All the FPGA tools by Xilinx work well under Linux and Vivado is actually quite pleasant to use. Almost all of the EDA tools can be scripted with TCL (cadence has a host of other DSL aswell) so you don’t need to use the GUI if you don’t want to.
Vivado is absolutely terrible, especially the GUI. Our toolchain at work is set up so that it can be entirely avoided, with developers only writing Verilog in their editor of choice, and calling make or pushing to Jenkins when they want results. And then they go home, as it takes a full day to build a product on our server farm. Sim/others is done with third-party products. I recall one Xilinx event where a Xilinx pr…
Vivado is absolutely terrible, especially the GUI. Our toolchain at work is set up so that it can be entirely avoided, with developers only writing Verilog in their editor of choice, and calling make or pushing to Jenkins when they want results. And then they go home, as it takes a full day to build a product on our server farm. Sim/others is done with third-party products.
That's how most companies do it in my experience (and I prefer it as well). That said, Vivado is leaps and bounds better than its predecessor (ISE). It may be horrible for HDL coding, but when you need to do timing analysis and floorplanning the GUI is really helpful and the integrated TCL command line makes it very flexible.
Tooling in FPGA-land is a sad story, unfortunately. It's stuck in the 90's. I've ranted enough times to feel I'm beating a dead horse, but it's frustrating to see how behind the times it is compared to software development. Just look at HDL IDEs as an example:
The vendor ones are worse than simple text editors, 3rd party IDEs cost an arm and a leg, while feature wise they are nowhere near their software counterparts. Take the most popular HDL IDEs (or should I say eclipse plugins?) and compare them with visual studio pro or jetbrains. The feature discrepancy is staggering (as is the price difference). We use Sigasi at work and while it's definitely better than a text editor, the basic version costs ~800$/yr and apart from error-checking, goto-definition and renaming there's not much else going on. For the same price you can get the whole jetbrains suite with a couple hundred dollars to spare.
Re: FPGAs becoming more SoC-like
#30Article says "CPU does not fit FPGA synthesis very well and uses almost whole thing". People serious about prototyping usually get daughterboards for FPGA and/or FPGA stacks specifically to prototype big things with CPUs. The buses can go outside of main FPGA with CPU and into other things. I know at least one big SoC project which went that way. I also think that having an ARM core in FPGA is a vendor lock in. For e…
> ARM itself is not very nice design from contemporary point of view. [...] they decided to use that ARM thing ARM CPUs are the de-facto standard in the embedded world (except for simple 8-bit MCUs), so what should Xilinx have done? Design their own, proprietary CPU architecture and ISA? Choose some other architecture with 2% market share? Both paths would have led to the immediate death of the whole product line. >…
> ARM CPUs are the de-facto standard in the embedded world (except for simple 8-bit MCUs), so what should Xilinx have done? Design their own, proprietary CPU architecture and ISA? Choose some other architecture with 2% market share? Both paths would have led to the immediate death of the whole product line.
Totally agree. IIRC, didn't Xilinx have another hard core CPU+FPGA design before the Zynq using a PowerPC? PPC is largely irrelevant these days. The high-performance embedded space is dominated by ARM today with x86 and PPC taking the rest. There's no way Xilinx would choose x86 with Intel owning Altera.
Maybe in 5-10 years RISC-V will start to eat some of ARM's share, but that remains to be seen.