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TSMC unveils 1.6nm process technology with backside power delivery

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Re: TSMC unveils 1.6nm process technology with backside power delivery

#191

Post by 3abiton »

Workaccount2 wrote: post #186
brennanpeterson wrote: post #173

Earlier quoted context omitted.

I am not sure where that would come from. There is nothing about dsa that means this. Dsa is one of many patterning assist technologies, just...an old one. Neat, but not 'new'. You use patterning assist to make smaller, more regular features, which is exactly what the 16a vs 18a refers to. That has somewhat less to do with performance, which is tied as much to material, stress, and interface parameters. Nothing gets…

DSA is what is going to make it possible for Intel to compete at all. Without it, they are going to have fancy machines in fancy foundries that are too expensive to attract any customers. To the best of my knowledge, DSA never made it out of the lab.

But still, what is stopping others from also developing DSA? I am not sure the technology alone will be Intel's savior. They've been on the decline for a while, ever since they took a jab at Nvidia for releasing CUDA, they demonstrated a narrow vision, consistently, and now they're playing a catch up game.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#192

Post by gregw2 »

blagie wrote: post #144
1oooqooq wrote: post #136

Earlier quoted context omitted.

now I'm even more confused. why start with Si if you're going to put a glass layer before anything else? why not start with glass right away?

Ergo, the TL;DR :) Even so, I oversimplified things a lot (a lot of the processes to leverage the silicon wafer, but some don't): https://en.wikipedia.org/wiki/Silicon_on_insulator One of the things to keep in mind is that a silicon wafer starts with a near-perfect silicon ingot crystal: https://en.wikipedia.org/wiki/Monocrystalline_silicon The level of purity and perfection there is a little bit crazy to conceive. I…

The demand for perfection is mildly ameliorated by having a few redundant circuits and microcode and then a software layer that can detect and workaround defects. If your GPU loses one if its 1000 integer math units, it doesn’t die, it just slows down for an operation that might otherwise use that one.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#193

Post by rcxdude »

AdamN wrote: post #78
blagie wrote: post #35

Earlier quoted context omitted.

ELI5: ICs are manufactured on silicon disks called wafers. Discs have two sides, and traditionally, everything was done on top. We can now do power on the bottom. This makes things go faster and use less power: * Power wires are big (and can be a bit crude). The bigger the better. Signal wires are small and precise. Smaller is generally better. * Big wires, if near signal wires, can interfere with them working optima…

There's still the question though of why they didn't do this decades ago - seems very obvious that this layout is better. What changed that made it possible only now and not earlier?

I think it's more that it's only necessary now. It's such a pain to make that you'll only do it given no other option. A lot of what modern processes are going was possible ages ago, but it was basically always better (in terms of ease for performance gain) to go smaller instead. Now that smaller doesn't help so much, you can see them pulling out all the other tricks in the book to try to improve (and costs going up as a result).

Re: TSMC unveils 1.6nm process technology with backside power delivery

#194

Post by rcxdude »

Detrytus wrote: post #153
blagie wrote: post #144

Earlier quoted context omitted.

Ergo, the TL;DR :) Even so, I oversimplified things a lot (a lot of the processes to leverage the silicon wafer, but some don't): https://en.wikipedia.org/wiki/Silicon_on_insulator One of the things to keep in mind is that a silicon wafer starts with a near-perfect silicon ingot crystal: https://en.wikipedia.org/wiki/Monocrystalline_silicon The level of purity and perfection there is a little bit crazy to conceive. I…

>> There are something like ≈100 billion transistors per IC for something like a high-end GPU, and a single failed transistor can destroy that fancy GPU. No, it can't thanks to this fancy marketing strategy where you sell faulty GPUs at lower price, as lower-tier model.

can is important there. Not all failures can be masked off. And this only makes the slightest of dent in the level of reliability you need in making any given transistor.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#195

Post by rcxdude »

onepointsixC wrote: post #148
SilverBirch wrote: post #111

Earlier quoted context omitted.

There are definitely going to be people taking a bet on the Intel foundry, but Intel has tried this before and it has worked badly.

Sounds like an easy short for you then.

Against OP maybe. Going short or long also depends on knowing what the market thinks will happen.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#196

Post by pjc50 »

kumarvvr wrote: post #133
futureshock wrote: post #59

Comments about the marketing driven nm measurements aside, this still looks like another solid advance for TSMC. They are already significantly ahead of Samsung and Intel on transistor density. TSMC is at 197 MTr/mm2 wile Samsung is at 150 MTr/mm2 and Intel is at 123 MTr/mm2. This 1.6nm process will put them around 230 MTr/mm2 by 2026. When viewed by this metric, Intel is really falling behind.

Its so hard to even fathom 200+ Million Transistors in 1 square millimeter ! And, to think, it's all done with light ! We live in interesting times !

Well, "extreme UV" these days. 13.5nm, larger than the "feature size". And even that required heroic effort in development of light sources and optics.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#197

Post by pjc50 »

polishdude20 wrote: post #181
jjk166 wrote: post #125

Earlier quoted context omitted.

The design optimization software for modern semiconductors is arguably the most advanced design software on earth with likely tens if not hundreds of millions of man-years put into it. It takes into account not only the complex physics that apply at the nano-scale but also the interplay of the various manufacturing steps and optimizes trillions of features. Every process change brings about new potential optimization…

How is this kind of software developed without becoming a massive pile of spaghetti code?

As someone who worked for a startup that was bought by Cadence: I have some bad news for you about that.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#198

Post by thsksbd »

Tagbert wrote: post #73
lostlogin wrote: post #53

Earlier quoted context omitted.

I’m sure you agree that the measurement given is a marketing term and is generally unhelpful beyond ‘it’s smaller than the current number’.

it also seems to be a roughly proportional change in density so why would it be unhelpful? Just because you can't point to a specific feature and say that is 1.6nm, doesn't make the label meaningless as so many try to assert. It is a label that represents a process that results in a specific transistor density. What label would you prefer?

... transistor density?

Re: TSMC unveils 1.6nm process technology with backside power delivery

#199

Post by thsksbd »

__alexs wrote: post #189
thsksbd wrote: post #105

Earlier quoted context omitted.

They're the ones specifying units.

I'm begging even 1 person in this thread to do even 5 minutes of research on where these numbers come from.

Let me see if I understand what this is.

It used to be the actual feature size which was quadratically proportional to transistor density.

Once feature size stopped being meaningful they continued using it by extrapolating from transistor density, ie whenever they would quadruple density they'd half this massive number. This, therefore, includes innovations like finfets and other " 2.5D" technologies

Is that largely correct? Because it's gross.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#200

Post by fennecbutt »

jjk166 wrote: post #125
ReptileMan wrote: post #65

Earlier quoted context omitted.

Not understanding chip design - but is it possible to get more computational bang with less transistors - are there some optimizations to be had? Better design that could compensate for bigger nodes?

The design optimization software for modern semiconductors is arguably the most advanced design software on earth with likely tens if not hundreds of millions of man-years put into it. It takes into account not only the complex physics that apply at the nano-scale but also the interplay of the various manufacturing steps and optimizes trillions of features. Every process change brings about new potential optimization…

Yeah, I don't think we really have any equivalent technology that is advanced or as detailed as chip making. Chip making is kind of the parent of pretty much every other technology we have at this point.
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