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IBM debuts sub-1 nanometer chip technology

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171–180 of 217 posts

Re: IBM debuts sub-1 nanometer chip technology

#171
post #75

Two big problems 1) NOBODY knows what IBM's definition of "sub 1nm" means 2) IBM bullshits so much more than anyone including Intel (remember the "teleportation" ads years ago) that nobody is going to waste time researching what they mean in reality

I know what it means. Something isn't automatically bullshit because it's outside your field of expertise.

People love to hate on IBM, ask why it is relevant today, while several of their beloved FOSS projects are in some way, form or fashion, made possible with IBM's money.

Re: IBM debuts sub-1 nanometer chip technology

#172
post #10

> logic technology can extend for the first time below the 1 nm node, advancing the era of angstrom-level scaling, where dimensions approach the size of individual atoms. While transistor nodes now refer to a generation of manufacturing technology versus an exact physical dimension, IBM’s 0.7 nm technology—also referred to as 7 angstroms—demonstrates how continued scaling remains possible. Continuing the well establi…

I believe it could be a stepping stone to significantly higher density in the future.

Re: IBM debuts sub-1 nanometer chip technology

#173

Earlier quoted context omitted.

Unlike marketing terms, "nm density" is actually useful measure. It describes density measure where you can compare it to planar transistors from the 28-nanometer (28 nm) node around 2010 to 2011 and before. A "0.7 nm" node has equivalent transistor density as if we could have shrunk standard flat transistor node down to 0.7 nanometers.

Density is mass per volume so how are you comparing it to a planar transistor? Your units don't even match.

All "density" means is that it's a quotient; I use spectral densities daily and that's "count per Hertz" which weirdly enough works out in normal units to be seconds.

Re: IBM debuts sub-1 nanometer chip technology

#174
post #91

Earlier quoted context omitted.

Not all densities is mass per volume. eg. population density.

Population density isn’t planar, eg, why cities are denser than towns: their centers are more than 2D.

Population density is literally measured over a planar metric: people/km^2

You are suggesting it's measured over a cube volume?

Re: IBM debuts sub-1 nanometer chip technology

#175

Earlier quoted context omitted.

Population density isn’t planar, eg, why cities are denser than towns: their centers are more than 2D.

Population density is literally measured over a planar metric: people/km^2 You are suggesting it's measured over a cube volume?

There are some really dense people

Re: IBM debuts sub-1 nanometer chip technology

#176

Earlier quoted context omitted.

Yes, and we're already there. We've been there for quite a while, in fact. Once you make the gate of a transistor small/thin enough, quantum effects take over. Electrons will randomly teleport into and through the gate causing the transistor to conduct when it shouldn't. I don't have numbers to hand, but it's on the order of a few atoms wide. There's really nothing that can be done about it either, as far as we know.…

>"The electron wave function will simply just appear wherever it wants (within the electron probability cloud)." I don't know which is more ridiculous, the fact that reality works like this, or, that a species of apes was able to figure this out.

I find it ridiculoua that we believe it is random probability instead of trying to find (and maybe later mitigate) the real sources of this randomness.

Re: IBM debuts sub-1 nanometer chip technology

#178
post #175

Earlier quoted context omitted.

Population density is literally measured over a planar metric: people/km^2 You are suggesting it's measured over a cube volume?

There are some really dense people

Some people are dense... now in three dimensions!

Re: IBM debuts sub-1 nanometer chip technology

#179
post #82

Earlier quoted context omitted.

As it can be seen from the photos, horizontally the features are much bigger than 5 nm. For silicon, the gate length of a FET has a lower limit somewhere between 10 nm and 15 nm. The current CMOS manufacturing processes have not reached the limit yet. For making smaller transistors, a transition to other semiconductor materials will be necessary. The vertical thicknesses of various layers may be of only a few nanomet…

The scale bar on the far right "photo" (micrograph?) doesn't make sense. It is only slightly less than half the scale bar on the middle photo (10 nm), but the image is clearly scaled up by much more than 2x. Individual silicon atoms are circled in the right photo, but the covalent radius of silicon is about 0.11 nm, so they should be much smaller if the scale bar is accurate.

The scale bar also got about 50% longer, which would imply a 3x zoom. That also seems about right based on the relative feature sizes. Same thing happened between the first and second image.

Re: IBM debuts sub-1 nanometer chip technology

#180
post #167

Earlier quoted context omitted.

Generations. Gen Alpha were born since the naming became detached from actual physical size. And parts of Gen Z (before) and Gen Beta (after).

Naming generations is a futile, arbitrary process, whereas the measurement unit for engineering processes should be precise and well defined?

Node sizes have been "generations" for a long time. The number is just the previous number divided by sqrt(2), rounded in an arbitrary direction. Sqrt(2) because reducing each dimension by that number leads to double the density, and it's non-obvious enough to sound like a real measurement
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