Hacker News Board Hacker News, browsed like a classic message board
Live data from Hacker News

Western Digital Plans to Ship More Than One Billion RISC-V Cores a Year

wdc.com

Post reply on HN
Print view View original

141–149 of 149 posts

Re: Western Digital Plans to Ship More Than One Billion RISC-V Cores a Year

#141

Post by anderspitman »

microcolonel wrote: post #82
anderspitman wrote: post #47

Earlier quoted context omitted.

I'm so excited that we're feasibly within a year or two of being able to develop embedded devices in Rust[0] on RISC-V microcontrollers [1] running on open source RTOSes also written in Rust[2]. It's currently already possible but still requires quite a bit of hacking. Plus the RF stacks (Bluetooth in particular) aren't there yet. What a time to be a developer. PS RISC-V on my X220 wouldn't hurt either. [0] http://bl…

> I'm so excited that we're feasibly within a year or two of being able to develop embedded devices in Rust[0] on RISC-V microcontrollers I'm happy to report that the future is yesterday![0][1] (sort of) > Plus the RF stacks (Bluetooth in particular) aren't there yet. Espressif is a RISC-V foundation member, and you know what that means. (hint: it rhymes with could-pie den-sill-hiccup )† :- ) [0]: https://abopen.com/…

Very nice. I actually hadn't realized Tensilica wasn't an Espressif technology. That would definitely be sweet if they switched to RISC-V

Re: Western Digital Plans to Ship More Than One Billion RISC-V Cores a Year

#142

Post by bluddy »

jabl wrote: post #118
jstewartmobile wrote: post #23

I guess this will be nice for industry, which may pass the savings along to the consumer, but as far as having auditable hardware that you have some control over, I don't see how this is any better than the ARM SoCs we already have--unless you're going to roll your own system on an FPGA. That, and I'm kind of disappointed everyone has drunk the RISC kool-aid. I think a lot of RISC "performance" has more to do with co…

> That, and I'm kind of disappointed everyone has drunk the RISC kool-aid. Well, the thing is, RISC "won" the "RISC vs. CISC" wars, in the sense that more or less every ISA designed since has been RISC [1]. Of course, CISC also won in the sense that x86 is still around, and Intel is of course fabulously successful. So at least for high-end cores designed with a big budget, the extra decoder complexity doesn't appear…

RISC won fully. Intel decodes its CISC into an internal RISC (micro-ops) in the hardware. And despite years and years of optimizations, they can't reduce their power requirements to ARM levels.

Re: Western Digital Plans to Ship More Than One Billion RISC-V Cores a Year

#143

Post by jstewartmobile »

bluddy wrote: post #142
jabl wrote: post #118

Earlier quoted context omitted.

> That, and I'm kind of disappointed everyone has drunk the RISC kool-aid. Well, the thing is, RISC "won" the "RISC vs. CISC" wars, in the sense that more or less every ISA designed since has been RISC [1]. Of course, CISC also won in the sense that x86 is still around, and Intel is of course fabulously successful. So at least for high-end cores designed with a big budget, the extra decoder complexity doesn't appear…

RISC won fully. Intel decodes its CISC into an internal RISC (micro-ops) in the hardware. And despite years and years of optimizations, they can't reduce their power requirements to ARM levels.

To be fair, Intel's old x86 ISA is kind of a mess, so microcoding everything back down to an internal RISC may have been the only way for them to even keep the thing manageable.

As CISC goes, 680x0 seemed a little saner to me, and it had more registers so you didn't have to go to memory as much. Back when I did MIPS programming, I remember getting more of a boost out of having more registers to work with than I did from the shorter instruction cycles.

So the variables are all very entangled... is the edge due to RISC? register count? 40 years of cruft (in Intel's case)? better compiler support? something else? I just feel like the whole thing deserves a little more investigation...

Re: Western Digital Plans to Ship More Than One Billion RISC-V Cores a Year

#144

Post by ori_b »

csense wrote: post #28

From the headline, I would guess WD is putting a user accessible CPU in each of their disk drives, idea being that if you have a CPU living close to the drive, then e.g. map+reduce workloads can be more efficiently executed. Instead of going with ARM or Intel, I guess the CPU's are using some less famous architecture called RISC-V. Then I read the article, and the article is so full of buzzwords and genericisms that…

Their drives already have ARM chips on them for the controller. Presumably, they're just going to swap that out for RISC-V, with few (if any) user visible changes.

Re: Western Digital Plans to Ship More Than One Billion RISC-V Cores a Year

#145

Post by kindfellow92 »

hajile wrote: post #130
kindfellow92 wrote: post #113

Earlier quoted context omitted.

ISAs can be patented. Intel is patenting their latest AVX/SSE instructions.

ISA spec is copyrighted. Instructions aren't patented directly. Instead, the best ways of implementing them are patented.

Seems like Microsoft is potentially being targeted for writing an x86 emulator https://newsroom.intel.com/editorials/x86-approaching-40-sti...

Re: Western Digital Plans to Ship More Than One Billion RISC-V Cores a Year

#146

Post by jabl »

jstewartmobile wrote: post #132
jabl wrote: post #118

Earlier quoted context omitted.

> That, and I'm kind of disappointed everyone has drunk the RISC kool-aid. Well, the thing is, RISC "won" the "RISC vs. CISC" wars, in the sense that more or less every ISA designed since has been RISC [1]. Of course, CISC also won in the sense that x86 is still around, and Intel is of course fabulously successful. So at least for high-end cores designed with a big budget, the extra decoder complexity doesn't appear…

Like you said ARM and x86, RISC and CISC, are the winners. I just wonder how much of that victory is due to circumstances of the time (like weak late-1980s compilers) and how much was due to clear technical superiority.

Well, if you're asking me, I'd say Intel is successful despite the technical shortcomings of the x86 ISA, not due to any technical advantages of it. Intel has the benefit of huge volumes (thanks to x86, yes), and they are very very good at chucking out big silicon wafers economically with low defect rates.

Thanks to those advantages, Intel can overcome the disadvantages of the ISA. Which aren't that big in their main markets, that is relatively high end cores.

Re: Western Digital Plans to Ship More Than One Billion RISC-V Cores a Year

#147

Post by CyberDildonics »

phkahler wrote: post #104
CyberDildonics wrote: post #96

Earlier quoted context omitted.

That would mean that the bandwidth from the hard drive is a large bottleneck, which I have a hard time believing is true.

AFAIK Doing error correction on 4K blocks of data is fairly non-trivial. Using custom instructions may be a benefit here too. https://www.seagate.com/tech-insights/advanced-format-4k-sec...

The parent post was talking about user accessible CPUs for running instructions closer to the data on the hard drive. Error correction being trivial or not, I don't think that is user facing software.

Re: Western Digital Plans to Ship More Than One Billion RISC-V Cores a Year

#148

Post by astrodust »

Taniwha wrote: post #108
astrodust wrote: post #62

Earlier quoted context omitted.

It wasn't that CISC won or that RISC lost, it was that the architectures got so blurry you couldn't tell one from the other. There's so much microcode in a CPU now that the instruction set is just the icing layer on the cake. Internally there's surprising amounts of commonality between PowerPC, ARM and x86 type chips. Plus PowerPC started to adopt CISC-like instructions, x86-64 started to adopt RISC-like features suc…

Actually most real RISC CPUs have no microcode, and if they do it's really just the same instruction set running out of an exception handler, not hardwired stuff on some other lower level private ISA

Is PowerPC still considered RISC? That instruction set has evolved considerably from the 601 days.

What is a "real" RISC CPU? By what definition?

Re: Western Digital Plans to Ship More Than One Billion RISC-V Cores a Year

#149

Post by Taniwha »

astrodust wrote: post #148
Taniwha wrote: post #108

Earlier quoted context omitted.

Actually most real RISC CPUs have no microcode, and if they do it's really just the same instruction set running out of an exception handler, not hardwired stuff on some other lower level private ISA

Is PowerPC still considered RISC? That instruction set has evolved considerably from the 601 days. What is a "real" RISC CPU? By what definition?

Well, there's lots of definitions - I'd include anything that generally has:

- single cycle ops - easy to decode ops (fixed size) - load/store architecture - lots of registers to reduce pressure on memory

Post reply on HN