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Intel completely disables AVX-512 on Alder Lake after all

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Re: Intel completely disables AVX-512 on Alder Lake after all

#121

Post by mhh__ »

square_usual wrote: post #44
codeflo wrote: post #11

If all of this was planned (and I’m not saying it is), that would have been very clever. It would work like this: 1. You “accidentally forget” to disable the feature in hardware. Given how competitive the market is, motherboard manufacturers can be relied upon to enable it in their “1337 OVERCLOCKZ” mode. No conspiracy is needed. 2. You “tolerate” this practice just long enough to win the critical initial wave of rev…

Is AVX-512 even useful in benchmarks? I thought it was mostly used for specialized workloads, and was basically useless for end users and gamers.

Some parts of the game would probably benefit a bit from 512 (also remember that it isn't just wider, it adds a lot of new operations entirely), but there simply isn't enough parallelism in the main loop of a game to make all that much difference.

Also "useful" and benchmarks do not mix well.

Re: Intel completely disables AVX-512 on Alder Lake after all

#122

Post by tymscar »

Fnoord wrote: post #20
SkeuomorphicBee wrote: post #10

Stuff like this is why I plan to never buy Intel ever again. I always disliked Intel's strategy for market segmentation by disabling specific instructions, I much prefer AMD's strategy of segmenting just by speed and number of cores. It is really annoying that with Intel you can't run the same program on the server and on your desktop, it makes development and testing a huge pain.

Nvidia do the same with disabling passthrough on consumer GPUs (gotta upsell Quatro). However I would say avoiding Intel completely is unnecessary. They're a good FOSS citizen when it boils to things like WLAN and GPU. Its just that with AMD, you can hardly go wrong on CPU and GPU side. Especially on Linux.

Not anymore! Nvidia gpus can be passed through just fine with no fixes. I use mine like that daily

Re: Intel completely disables AVX-512 on Alder Lake after all

#123

Post by ashtonkem »

codeflo wrote: post #11

If all of this was planned (and I’m not saying it is), that would have been very clever. It would work like this: 1. You “accidentally forget” to disable the feature in hardware. Given how competitive the market is, motherboard manufacturers can be relied upon to enable it in their “1337 OVERCLOCKZ” mode. No conspiracy is needed. 2. You “tolerate” this practice just long enough to win the critical initial wave of rev…

> Very few “evil schemes” exist in reality because people aren’t all that clever (and all that evil).

Also, groups of people are really bad at keeping secrets. In my experience most orgs that do bad things find a way to make everyone think that it’s either actually a good thing, or that someone else is responsible for it. If you make people think there’s a dark secret, they’ll tell eventually.

Re: Intel completely disables AVX-512 on Alder Lake after all

#124

Post by ncmncm »

timpattinson wrote: post #113
flyinghamster wrote: post #61

Earlier quoted context omitted.

The Core 2 Quad Q8200 was what did it for me. I had intended to build a system to play with virtual machines, only to find after I built it up that the Q8200 didn't have VT-x - something that was NOT noted in the store display. I put it in an Intel-branded motherboard as well, and that turned out to be one of the few motherboards I've had that failed prematurely. Since then, the only Intels I've bought since then hav…

to be fair, that's unavoidable with AVX-512, you can't underestimate how much power it draws compared to non-vectorised instructions. That's why Prime95 is such an effective stress test and draws 150% of the power that Cinebench R20 does for example.

You can, in fact, underestimate that, and most people who guess do.

Re: Intel completely disables AVX-512 on Alder Lake after all

#125

Post by mhh__ »

_xnmw wrote: post #41

Between shenanigans like this and Spectre/Meltdown mitigations giving me a ~20% performance hit [1], I avoid Intel like the plague if I have the choice. [1] https://arxiv.org/pdf/1807.08703.pdf

Pretty crap reasoning then. Intel never ever marketed these as having AVX-512 and unless you are running a Xeon from 2012 like the paper you've linked a modern CPU (note, any desktop class CPU) will only be vulnerable to some bits of Spectre and not meltdow

Re: Intel completely disables AVX-512 on Alder Lake after all

#126

Post by PragmaticPulp »

hajile wrote: post #118
PragmaticPulp wrote: post #86

Earlier quoted context omitted.

> 2. You “tolerate” this practice just long enough to win the critical initial wave of reviews and benchmarks. Interested buyers will look at those charts for years to come. That’s not what happened here. The AVX-512 instructions not only weren’t enabled by default, they couldn’t be enabled at all unless you went out of your way to disable the efficiency cores completely. They also wouldn’t benefit your workload unle…

> The AVX-512 instructions not only weren’t enabled by default, they couldn’t be enabled at all unless you went out of your way to disable the efficiency cores completely. They also wouldn’t benefit your workload unless disabling those extra cores was offset by the AVX-512 instructions on the remaining cores. If your code benefits from AVX-512, it'll probably benefit from turning off the efficiency cores too. Sixteen…

> If your code benefits from AVX-512, it'll probably benefit from turning off the efficiency cores too.

Maybe if you have a poorly parallelized problem where the bulk of the code is spent in AVX-512 instructions and you don’t ever do anything else on the computer, but that’s going to be rare for any consumer.

> The real solution would be for Intel to detect the presence of AVX-512 instructions then automatically and unconditionally pin the thread to the big cores. It wouldn't be hard either, just catch the unknown instruction exception and see if it is AVX-512 then move the thread.

“It wouldn’t be hard” is a huge understatement. This is OS-level support, not something Intel can just do inside the CPU. And operating system vendors and developers are still catching up to basic Alder Like scheduler support without AVX-512 handing, so it’s not reasonable to suggest this would be easy.

Re: Intel completely disables AVX-512 on Alder Lake after all

#127

Post by makomk »

PragmaticPulp wrote: post #67
marcan_42 wrote: post #38

Earlier quoted context omitted.

Don't forget it's not just instruction sets; Intel is the reason we don't have ECC RAM on desktops. Every other high density storage technology has used error correction for a decade or two, but we're still sitting here pretending we can have 512 billion bits of perfect memory sitting around that will never go wrong, because Intel fuse it off on desktop chips. I guess only servers need to be reliable. AMD supports EC…

> Intel is the reason we don't have ECC RAM on desktops. Intel has offered ECC support in a lot of their low-end i3 parts for a long time. They’re popular for budget server builds for this reason. The real reason people don’t use ECC is because they don’t like paying extra for consumer builds. That’s all. ECC requires more chips, more traces, and more expense. Consumers can’t tell if there’s a benefit, so they skip i…

As far as I can tell, Intel only offered ECC on a small handful of i3 parts that mainly seemed to be marketed to NAS manufacturers, likely because they were otherwise giving up that market entirely to competitors like AMD. They really don't seem to be interested in offering it as an option on consumer desktops.

Re: Intel completely disables AVX-512 on Alder Lake after all

#128

Post by leeter »

mhh__ wrote: post #121
square_usual wrote: post #44

Earlier quoted context omitted.

Is AVX-512 even useful in benchmarks? I thought it was mostly used for specialized workloads, and was basically useless for end users and gamers.

Some parts of the game would probably benefit a bit from 512 (also remember that it isn't just wider, it adds a lot of new operations entirely), but there simply isn't enough parallelism in the main loop of a game to make all that much difference. Also "useful" and benchmarks do not mix well.

For games generally those parts can be shifted to the GPU because they feed the rendering pipeline anyway. Doing so has other benefits of lowering latency for that data to be picked up by the graphics bits already there etc. Also the clock speed penalty for AVX512 is pretty steep so unless you're going to do a lot of AVX512 it really doesn't make sense either. Games generally aren't using double precision either which is the AVX512 bread and butter. To make it more fun even if they were... a 4x4 matrix is composed of 256bit elements so the vast majority of register usage wouldn't be 512 bit anyway. The main benefit would be the new instructions more than the register width.

Long story short: Games generally aren't doing enough AVX to really benefit from it as implemented. They can be quite bursty in their use. Not to mention that Not every CPU even has AVX (because apparently Pentium Gold is a thing) even today.

If Intel convinced AMD to pick up the 256 bit versions and removed the clock speed penalties I could see them getting more use. But at the moment it's really just a feature for the HFT market primarily and even they are extremely careful in use because of the clock speed penalty. To the point they will literally benchmark both ways to make sure the penalty is overcome by the throughput.

Re: Intel completely disables AVX-512 on Alder Lake after all

#129

Post by vanderZwan »

marcan_42 wrote: post #96
formerly_proven wrote: post #89

Earlier quoted context omitted.

> Don't forget it's not just instruction sets; Intel is the reason we don't have ECC RAM on desktops. Every other high density storage technology has used error correction for a decade or two, but we're still sitting here pretending we can have 512 billion bits of perfect memory sitting around that will never go wrong, because Intel fuse it off on desktop chips. I guess only servers need to be reliable. And not just…

Yup. PCIe will practically run over wet string, thanks to error detection and retransmits and other reasons, but try having a marginal DRAM bus and see how much fun that is...

Could be a fun way to test and demonstrate robustness of various parts of computer hardware, actually. It's already been done with ADSL for example:

[0] https://www.revk.uk/2017/12/its-official-adsl-works-over-wet...

Re: Intel completely disables AVX-512 on Alder Lake after all

#130

Post by gambiting »

marcan_42 wrote: post #119
gambiting wrote: post #68

Earlier quoted context omitted.

Sure, but that's a customer expectation vs legal obligation. Like, my sister bought the new M1 MacBook Air, only to discover that it doesn't support dual external screens - while her previous Air did. So there was absolutely an expectation there that any new MacBook Air would also support dual screens, right? But, at the end of the day - it is mentioned in the spec sheet. She could have checked. Just assuming that a…

The difference is dual screens don't work on the M1 MBA because it physically only has two display controllers in the silicon, one of them wired to the internal panel, and the other muxed to the two TB ports. The M1 Pro has two external display controllers, and the M1 Max four. I can show you where they are on the die shots, and that it's not artificial crippling. But what Intel is doing here is disabling existing si…

Sure, but as a customer that's irrelevant, right? You had a MacBook Air, used it with two displays, then you buy a new MacBook Air and bam, it doesn't work with two displays. The technical nitty gritty is not really relevant - at least the comment I was replying to sounded this way. That what the customer expects is more important than what is on the spec sheet? The fact that previous Intel CPU supported AVX-512, and the new one doesn't - so whether this fact is or isn't mentioned in the spec sheet is not important, because what the customer expects should be ultimately what decides what is "ok".
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