> That, and I'm kind of disappointed everyone has drunk the RISC kool-aid.
Well, the thing is, RISC "won" the "RISC vs. CISC" wars, in the sense that more or less every ISA designed since has been RISC [1]. Of course, CISC also won in the sense that x86 is still around, and Intel is of course fabulously successful. So at least for high-end cores designed with a big budget, the extra decoder complexity doesn't appear to hurt that much. But if you're doing a new ISA from scratch, no need to repeat the mistakes of the past.
Now, one can always hope that something better comes around. I'm not particularly hopeful that stack machines would be it; Forth has been around for how many decades now, if it would be such a good idea I think it would have already made its breakthrough. But there's plenty of research-y stuff out there (I admit to not being very familiar with most of it). Such as asynchronous (clock-less) logic, non-binary (ternary) logic, Mill(?), reversible computing, dataflow architecture, neuromorphic computing, quantum computing, graph reduction machines, and whatnot.
[1] In the sense of
- Load-store architecture
- fixed-length instructions (yes, ARM thumb and RISC-V C slightly break this, but still)
- ISA designed primarily as a compiler target rather than for human ASM programmers.